Variable-latency design by function speculation

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 1704-1709

  Baneres D ^a   Cortadella, J ^b   Kishinevsky, M ^c  

^a UNIVERSITAT OBERTA DE CATALUNYA   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS;

CRITICAL NODE; INPUT PATTERNS; LARGE CIRCUITS; MULTI CYCLE; SELECTED EXAMPLES; SMALL AREA; TIMING ANALYSIS; VARIABLE LATENCIES;

DELAY CIRCUITS;

EID: 70350048803     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090937     Document Type: Conference Paper

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