-
1
-
-
21644472427
-
Managing wire delay in large chip multiprocessor caches
-
B. M. Beckmann and D. A. Wood, "Managing wire delay in large chip multiprocessor caches", IEEE MICRO 37, pp. 319-330, 2004
-
(2004)
IEEE MICRO
, vol.37
, pp. 319-330
-
-
Beckmann, B.M.1
Wood, D.A.2
-
2
-
-
4043150092
-
Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip
-
D. Bertozzi and L. Benini, "Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip", IEEE Circuits and Systems Magazine, Vol. 4, Issue 2, pp. 18-31, 2004
-
(2004)
IEEE Circuits and Systems Magazine
, vol.4
, Issue.2
, pp. 18-31
-
-
Bertozzi, D.1
Benini, L.2
-
3
-
-
9544239365
-
Cost Considerations in Network on Chip
-
E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "Cost Considerations in Network on Chip", Integration - the VLSI Journal, Vol. 38, pp. 19-42, 2004
-
(2004)
Integration - the VLSI Journal
, vol.38
, pp. 19-42
-
-
Bolotin, E.1
Cidon, I.2
Ginosar, R.3
Kolodny, A.4
-
4
-
-
1242309790
-
QNoC: QoS Architecture and Design Process for Network on Chip
-
E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "QNoC: QoS Architecture and Design Process for Network on Chip", Journal of Systems Architecture, Vol. 50, pp. 105-128, 2004
-
(2004)
Journal of Systems Architecture
, vol.50
, pp. 105-128
-
-
Bolotin, E.1
Cidon, I.2
Ginosar, R.3
Kolodny, A.4
-
5
-
-
36348965353
-
The Power of Priority: NoC based Distributed Cache Coherency
-
E. Bolotin, Z. Guz, I. Cidon, R. Ginosar, and A. Kolodny, "The Power of Priority: NoC based Distributed Cache Coherency", Proc. First Int. Symposium on Networks-on-Chip (NOCS), pp. 117-126, 2007
-
(2007)
Proc. First Int. Symposium on Networks-on-Chip (NOCS)
, pp. 117-126
-
-
Bolotin, E.1
Guz, Z.2
Cidon, I.3
Ginosar, R.4
Kolodny, A.5
-
6
-
-
27344456043
-
AEthereal Network on Chip: Concepts, Architectures, and Implementations
-
K. Goossens, J. Dielissen, and A. Radulescu, "AEthereal Network on Chip: Concepts, Architectures, and Implementations", IEEE Design and Test of Computers, pp. 414-421, 2005
-
(2005)
IEEE Design and Test of Computers
, pp. 414-421
-
-
Goossens, K.1
Dielissen, J.2
Radulescu, A.3
-
7
-
-
34547657571
-
A Domain-Specific On-Chip Network Design for Large Scale Cache Systems
-
Y. Jin, E. J. Kim, and K H. Yum, "A Domain-Specific On-Chip Network Design for Large Scale Cache Systems", Proc. 13th Int. Symp. on High-Performance Computer Architecture, pp. 318-327, 2007
-
(2007)
Proc. 13th Int. Symp. on High-Performance Computer Architecture
, pp. 318-327
-
-
Jin, Y.1
Kim, E.J.2
Yum, K.H.3
-
8
-
-
0036949388
-
An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches
-
C. Kim, D. Burger, and S.W. Keckler, "An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches", 10th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 211-222, 2002
-
(2002)
10th International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 211-222
-
-
Kim, C.1
Burger, D.2
Keckler, S.W.3
-
9
-
-
10744231529
-
Nonuniform Cache Architectures for Wire Delay Dominated on-Chip Caches
-
C. Kim, D. Burger, and S.W. Keckler, "Nonuniform Cache Architectures for Wire Delay Dominated on-Chip Caches", IEEE Micro, 23:6, pp. 99-107, 2003
-
(2003)
IEEE Micro
, vol.23
, Issue.6
, pp. 99-107
-
-
Kim, C.1
Burger, D.2
Keckler, S.W.3
-
11
-
-
33748554106
-
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
-
T. D. Richardson, C. Nicopoulos, D. Park, V. Narayanan, Y. Xie, C. Das, V. Degalahal, "A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks", Proc. 19th International Conference on VLSI Design, pp. 657-664, 2006
-
(2006)
Proc. 19th International Conference on VLSI Design
, pp. 657-664
-
-
Richardson, T.D.1
Nicopoulos, C.2
Park, D.3
Narayanan, V.4
Xie, Y.5
Das, C.6
Degalahal, V.7
-
12
-
-
34047123275
-
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips
-
S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. De Micheli, "A Methodology for Mapping Multiple Use-Cases onto Networks on Chips", Proc. Design, Automation and Test in Europe (DATE) 2006
-
(2006)
Proc. Design, Automation and Test in Europe (DATE)
-
-
Murali, S.1
Coenen, M.2
Radulescu, A.3
Goossens, K.4
De Micheli, G.5
-
15
-
-
70349800138
-
-
ITRS, International Technology Roadmap for Semiconductors
-
ITRS - International Technology Roadmap for Semiconductors, http://www.itrs.net
-
-
-
-
17
-
-
0036469676
-
Simics: A full system simulation platform
-
P. S. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, and G. Hallberg, "Simics: A full system simulation platform", IEEE Computer, 35(2):50-58, 2002
-
(2002)
IEEE Computer
, vol.35
, Issue.2
, pp. 50-58
-
-
Magnusson, P.S.1
Christensson, M.2
Eskilson, J.3
Forsgren, D.4
Hallberg, G.5
-
18
-
-
0029179077
-
The SPLASH-2 Programs: Characterization and Methodological Considerations
-
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta., "The SPLASH-2 Programs: Characterization and Methodological Considerations", In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 24-37, 1995
-
(1995)
Proceedings of the 22nd Annual International Symposium on Computer Architecture
, pp. 24-37
-
-
Woo, S.C.1
Ohara, M.2
Torrie, E.3
Singh, J.P.4
Gupta, A.5
-
20
-
-
3042640630
-
A Comparison of Five Different Multiprocessor SoC Bus Architectures
-
K. K. Ryu, E. Shin, and V. J. Moony, "A Comparison of Five Different Multiprocessor SoC Bus Architectures", Euromicro, 2001
-
(2001)
Euromicro
-
-
Ryu, K.K.1
Shin, E.2
Moony, V.J.3
-
21
-
-
70349833861
-
-
AMBA System Architecture
-
AMBA System Architecture, http://www.arm.com/products/solutions/ AMBAHomePage.html
-
-
-
-
22
-
-
0004093751
-
-
CoreConnect Bus Architecture, http://www-01.ibm.com/chips/techlib/ techlib.nsf/productfamilies/Coreconnect-Bus-Architecture
-
CoreConnect Bus Architecture
-
-
|