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Volumn , Issue , 2009, Pages 173-182

Best of both worlds: A bus enhanced NoC (BENoC)

Author keywords

[No Author keywords available]

Indexed keywords

BROADCAST AND MULTICAST; CACHE ACCESS; ENERGY CONSUMPTION; HIGH THROUGHPUT; INTEGRAL PART; LOW POWER; LOW-LATENCY; MULTI PROCESSOR SYSTEMS; MULTICAST OPERATIONS; MULTIHOP; NOC ARCHITECTURES; NONUNIFORM; POTENTIAL BENEFITS; SENSITIVE SIGNALS; SHARED BUS;

EID: 70349846150     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2009.5071465     Document Type: Conference Paper
Times cited : (28)

References (22)
  • 1
    • 21644472427 scopus 로고    scopus 로고
    • Managing wire delay in large chip multiprocessor caches
    • B. M. Beckmann and D. A. Wood, "Managing wire delay in large chip multiprocessor caches", IEEE MICRO 37, pp. 319-330, 2004
    • (2004) IEEE MICRO , vol.37 , pp. 319-330
    • Beckmann, B.M.1    Wood, D.A.2
  • 2
    • 4043150092 scopus 로고    scopus 로고
    • Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip
    • D. Bertozzi and L. Benini, "Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip", IEEE Circuits and Systems Magazine, Vol. 4, Issue 2, pp. 18-31, 2004
    • (2004) IEEE Circuits and Systems Magazine , vol.4 , Issue.2 , pp. 18-31
    • Bertozzi, D.1    Benini, L.2
  • 9
    • 10744231529 scopus 로고    scopus 로고
    • Nonuniform Cache Architectures for Wire Delay Dominated on-Chip Caches
    • C. Kim, D. Burger, and S.W. Keckler, "Nonuniform Cache Architectures for Wire Delay Dominated on-Chip Caches", IEEE Micro, 23:6, pp. 99-107, 2003
    • (2003) IEEE Micro , vol.23 , Issue.6 , pp. 99-107
    • Kim, C.1    Burger, D.2    Keckler, S.W.3
  • 15
    • 70349800138 scopus 로고    scopus 로고
    • ITRS, International Technology Roadmap for Semiconductors
    • ITRS - International Technology Roadmap for Semiconductors, http://www.itrs.net
  • 20
    • 3042640630 scopus 로고    scopus 로고
    • A Comparison of Five Different Multiprocessor SoC Bus Architectures
    • K. K. Ryu, E. Shin, and V. J. Moony, "A Comparison of Five Different Multiprocessor SoC Bus Architectures", Euromicro, 2001
    • (2001) Euromicro
    • Ryu, K.K.1    Shin, E.2    Moony, V.J.3
  • 21
    • 70349833861 scopus 로고    scopus 로고
    • AMBA System Architecture
    • AMBA System Architecture, http://www.arm.com/products/solutions/ AMBAHomePage.html
  • 22
    • 0004093751 scopus 로고    scopus 로고
    • CoreConnect Bus Architecture, http://www-01.ibm.com/chips/techlib/ techlib.nsf/productfamilies/Coreconnect-Bus-Architecture
    • CoreConnect Bus Architecture


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.