-
1
-
-
20444496778
-
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
-
Jun
-
A. H. Ajami, K. Banerjee, and M. Pedram, "Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.24, no.6, pp. 849-861, Jun. 2005.
-
(2005)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.24
, Issue.6
, pp. 849-861
-
-
Ajami, A.H.1
Banerjee, K.2
Pedram, M.3
-
2
-
-
33947715600
-
IPC considered harmful for multiprocessor workloads
-
Jul./Aug
-
A. R. Alameldeen and D. A. Wood, "IPC considered harmful for multiprocessor workloads," IEEE Micro, vol.26, no.4, pp. 8-17, Jul./Aug. 2006.
-
(2006)
IEEE Micro
, vol.26
, Issue.4
, pp. 8-17
-
-
Alameldeen, A.R.1
Wood, D.A.2
-
3
-
-
49549092447
-
Reliability-aware design for nanometer- scale devices
-
D. Atienza, G. D. Micheli, L. Benini, J. L. Ayala, P. G. D. Valle, M. DeBole, and V. Narayanan, "Reliability-aware design for nanometer- scale devices," in Proc. ASPDAC, 2008, pp. 549-554.
-
(2008)
Proc. ASPDAC
, pp. 549-554
-
-
Atienza, D.1
Micheli, G.D.2
Benini, L.3
Ayala, J.L.4
Valle, P.G.D.5
Debole, M.6
Narayanan, V.7
-
4
-
-
34547217005
-
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
-
D. Atienza, P. D. Valle, G. Paci, F. Poletti, L. Benini, G. D. Micheli, and J. M. Mendias, "A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip," in Proc. DAC, 2006, pp. 618-623.
-
(2006)
Proc. DAC
, pp. 618-623
-
-
Atienza, D.1
Valle, P.D.2
Paci, G.3
Poletti, F.4
Benini, L.5
Micheli, G.D.6
Mendias, J.M.7
-
5
-
-
2642548834
-
Network-oriented full-system simulation using M5
-
N. L. Binkert, E. G. Hallnor, and S. K. Reinhardt, "Network-oriented full-system simulation using M5," in Proc. Workshop CAECW, 2003, pp. 36-43.
-
(2003)
Proc. Workshop CAECW
, pp. 36-43
-
-
Binkert, N.L.1
Hallnor, E.G.2
Reinhardt, S.K.3
-
6
-
-
0033719421
-
Wattch: A framework for architectural-level power analysis and optimizations
-
D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations," in Proc. ISCA, 2000, pp. 83-94.
-
(2000)
Proc. ISCA
, pp. 83-94
-
-
Brooks, D.1
Tiwari, V.2
Martonosi, M.3
-
7
-
-
34548023929
-
Cooperative cache partitioning for chip multiprocessors
-
J. Chang and G. S. Sohi, "Cooperative cache partitioning for chip multiprocessors," in Proc. ICS, 2007, pp. 242-252.
-
(2007)
Proc. ICS
, pp. 242-252
-
-
Chang, J.1
Sohi, G.S.2
-
8
-
-
57849133498
-
Proactive temperature balancing for low cost thermal management in MPSoCs
-
A. K. Coskun, T. Rosing, and K. Gross, "Proactive temperature balancing for low cost thermal management in MPSoCs," in Proc. ICCAD, 2008, pp. 250-257.
-
(2008)
Proc. ICCAD
, pp. 250-257
-
-
Coskun, A.K.1
Rosing, T.2
Gross, K.3
-
9
-
-
34548335311
-
Temperature aware task scheduling in MPSoCs
-
A. K. Coskun, T. Rosing, and K. Whisnant, "Temperature aware task scheduling in MPSoCs," in Proc. DATE, 2007, pp. 1659-1664.
-
(2007)
Proc. DATE
, pp. 1659-1664
-
-
Coskun, A.K.1
Rosing, T.2
Whisnant, K.3
-
10
-
-
70349732333
-
Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors
-
A. K. Coskun, R. Strong, D. Tullsen, and T. S. Rosing, "Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors," in Proc. SIGMETRICS/Performance, 2009, pp. 169-180.
-
(2009)
Proc. SIGMETRICS/Performance
, pp. 169-180
-
-
Coskun, A.K.1
Strong, R.2
Tullsen, D.3
Rosing, T.S.4
-
11
-
-
33845904113
-
Techniques for multicore thermal management: Classification and new exploration
-
J. Donald and M. Martonosi, "Techniques for multicore thermal management: Classification and new exploration," in Proc. ISCA, 2006, pp. 78-88.
-
(2006)
Proc. ISCA
, pp. 78-88
-
-
Donald, J.1
Martonosi, M.2
-
12
-
-
12344252114
-
Heat-and-run: Leverging SMT and CMP to manage power density through the operating system
-
M. Gomaa, M. D. Powell, and T. N. Vijaykumar, "Heat-and-run: Leverging SMT and CMP to manage power density through the operating system," in Proc. ASPLOS, 2004, pp. 260-270.
-
(2004)
Proc. ASPLOS
, pp. 260-270
-
-
Gomaa, M.1
Powell, M.D.2
Vijaykumar, T.N.3
-
13
-
-
34548334470
-
Electronic prognostics through continuous system telemetry
-
Apr
-
K. Gross, K. Whisnant, and A. Urmanov, "Electronic prognostics through continuous system telemetry," in Proc. MFPT, Apr. 2006, pp. 53-62.
-
(2006)
Proc. MFPT
, pp. 53-62
-
-
Gross, K.1
Whisnant, K.2
Urmanov, A.3
-
14
-
-
0026103647
-
Sequential probability ratio test for nuclear plant component surveillance
-
Feb
-
K. C. Gross and K. E. Humenik, "Sequential probability ratio test for nuclear plant component surveillance," Nucl. Technol., vol.93, no.2, pp. 131-137, Feb. 1991.
-
(1991)
Nucl. Technol.
, vol.93
, Issue.2
, pp. 131-137
-
-
Gross, K.C.1
Humenik, K.E.2
-
15
-
-
33646909655
-
Thermal-aware task allocation and scheduling for embedded systems
-
DOI 10.1109/DATE.2005.310, 1395698, Proceedings - Design, Automation and Test in Europe, DATE '05
-
W.-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "Thermal-aware task allocation and scheduling for embedded systems," in Proc. DATE, 2005, pp. 898-899. (Pubitemid 44172114)
-
(2005)
Proceedings -Design, Automation and Test in Europe, DATE '05
, vol.II
, pp. 898-899
-
-
Hung, W.-L.1
Xie, Y.2
Vijaykrishnan, N.3
Kandemir, M.4
Irwin, M.J.5
-
16
-
-
36949001469
-
An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget
-
C. Isci, A. Buyuktosunoglu, C. CHer, P. Bose, and M. Martonosi, "An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget," in Proc. MICRO, 2006, pp. 347-358.
-
(2006)
Proc. MICRO
, pp. 347-358
-
-
Isci, C.1
Buyuktosunoglu, A.2
Cher, C.3
Bose, P.4
Martonosi, M.5
-
17
-
-
36949023020
-
Live, runtime phase monitoring and prediction on real systems with application to dynamic power management
-
C. Isci, G. Contreras, and M. Martonosi, "Live, runtime phase monitoring and prediction on real systems with application to dynamic power management," in Proc. 39th MICRO, 2006, pp. 359-370.
-
(2006)
Proc. 39th MICRO
, pp. 359-370
-
-
Isci, C.1
Contreras, G.2
Martonosi, M.3
-
18
-
-
84893381946
-
Failure mechanisms and models for semiconductor devices
-
"Failure mechanisms and models for semiconductor devices," JEDEC Publication JEP122C. [Online]. Available: http://www.jedec.org
-
JEDEC Publication JEP122C
-
-
-
19
-
-
0028452732
-
Competitive randomized algorithms for nonuniform problems
-
Jun
-
A. Karlin, M. Manesse, L. McGeoch, and S. Owicki"Competitive randomized algorithms for nonuniform problems," Algorithmica, vol.11, no.6, pp. 542-571, Jun. 1994.
-
(1994)
Algorithmica
, vol.11
, Issue.6
, pp. 542-571
-
-
Karlin, A.1
Manesse, M.2
McGeoch, L.3
Owicki, S.4
-
20
-
-
34547143358
-
HybDTM: A coordinated hardware-software approach for dynamic thermal management
-
A. Kumar, L. Shang, L.-S. Peh, and N. K. Jha, "HybDTM: A coordinated hardware-software approach for dynamic thermal management," in Proc. DAC, 2006, pp. 548-553.
-
(2006)
Proc. DAC
, pp. 548-553
-
-
Kumar, A.1
Shang, L.2
Peh, L.-S.3
Jha, N.K.4
-
21
-
-
33846227016
-
A power-efficient high-throughput 32-thread SPARC processor
-
Jan
-
A. Leon, L. Jinuk, K. Tam, W. Bryg, F. Schumacher, P. Kongetira, D. Weisner, and A. Strong, "A power-efficient high-throughput 32-thread SPARC processor," IEEE J. Solid-State Circuits, vol.42, no.1, pp. 7-16, Jan. 2007.
-
(2007)
IEEE J. Solid-State Circuits
, vol.42
, Issue.1
, pp. 7-16
-
-
Leon, A.1
Jinuk, L.2
Tam, K.3
Bryg, W.4
Schumacher, F.5
Kongetira, P.6
Weisner, D.7
Strong, A.8
-
24
-
-
34247581920
-
Power and reliability management of SoCs
-
Apr
-
T. S. Rosing, K. Mihic, and G. D. Micheli, "Power and reliability management of SoCs," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.15, no.4, pp. 391-403, Apr. 2007.
-
(2007)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.15
, Issue.4
, pp. 391-403
-
-
Rosing, T.S.1
Mihic, K.2
Micheli, G.D.3
-
25
-
-
34047117937
-
Communication-aware allocation and scheduling framework for stream- oriented multi-processor system-on-chip
-
M. Ruggiero, A. Guerri, D. Bertozzi, F. Poletti, and M. Milano, "Communication-aware allocation and scheduling framework for stream- oriented multi-processor system-on-chip," in Proc. DATE, 2006, pp. 3-8.
-
(2006)
Proc. DATE
, pp. 3-8
-
-
Ruggiero, M.1
Guerri, A.2
Bertozzi, D.3
Poletti, F.4
Milano, M.5
-
26
-
-
49249086142
-
Larrabee: A many-core x86 architecture for visual computing
-
L. Seiler, D. Carmean, E. Sprangle, T. Forsyth, M. Abrash, P. Dubey, S. Junkins, A. Lake, J. Sugerman, R. Cavin, R. Espasa, E. Grochowski, T. Juan, and P. Hanrahan, "Larrabee: A many-core x86 architecture for visual computing," in Proc. ACM SIGGRAPH, 2008, pp. 1-15.
-
(2008)
Proc. ACM SIGGRAPH
, pp. 1-15
-
-
Seiler, L.1
Carmean, D.2
Sprangle, E.3
Forsyth, T.4
Abrash, M.5
Dubey, P.6
Junkins, S.7
Lake, A.8
Sugerman, J.9
Cavin, R.10
Espasa, R.11
Grochowski, E.12
Juan, T.13
Hanrahan, P.14
-
27
-
-
0036953769
-
Automatically characterizing large scale program behavior
-
T. Sherwood, G. H. E. Perelman, and B. Calder, "Automatically characterizing large scale program behavior," in Proc. ASPLOS, 2002, pp. 45-57.
-
(2002)
Proc. ASPLOS
, pp. 45-57
-
-
Sherwood, T.1
Perelman, G.H.E.2
Calder, B.3
-
28
-
-
0038684860
-
Temperature-aware microarchitecture
-
K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, "Temperature-aware microarchitecture," in Proc. ISCA, 2003, pp. 2-13.
-
(2003)
Proc. ISCA
, pp. 2-13
-
-
Skadron, K.1
Stan, M.2
Huang, W.3
Velusamy, S.4
Sankaranarayanan, K.5
Tarjan, D.6
-
30
-
-
4644313547
-
The case for lifetime reliability-aware microprocessors
-
J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, "The case for lifetime reliability-aware microprocessors," in Proc. ISCA, 2004, pp. 276-287.
-
(2004)
Proc. ISCA
, pp. 276-287
-
-
Srinivasan, J.1
Adve, S.V.2
Bose, P.3
Rivers, J.A.4
-
31
-
-
1542269367
-
Full-chip leakage estimation considering power supply and temperature variations
-
H. Su, F. Liu, A. Devgan, E. Acar, and S. Nassif, "Full-chip leakage estimation considering power supply and temperature variations," in Proc. ISLPED, 2003, pp. 78-83.
-
(2003)
Proc. ISLPED
, pp. 78-83
-
-
Su, H.1
Liu, F.2
Devgan, A.3
Acar, E.4
Nassif, S.5
-
32
-
-
34547664408
-
-
HP Lab., Palo Alto, CA, Tech. Rep. HPL
-
D. Tarjan, S. Thoziyoor, and N. P. Jouppi, "CACTI 4.0," HP Lab., Palo Alto, CA, Tech. Rep. HPL-2006-2086, 2006.
-
(2006)
CACTI 4.0
, pp. 2006-2086
-
-
Tarjan, D.1
Thoziyoor, S.2
Jouppi, N.P.3
-
33
-
-
49549084422
-
A third-generation 65 nm 16-core 32- thread plus 32-scout-thread CMT SPARC processor
-
M. Tremblay and S. Chaudhry, "A third-generation 65 nm 16-core 32- thread plus 32-scout-thread CMT SPARC processor," in Proc. ISSCC, 2008, pp. 82-83.
-
(2008)
Proc. ISSCC
, pp. 82-83
-
-
Tremblay, M.1
Chaudhry, S.2
-
34
-
-
0000193326
-
Optimum character of the sequential probability ratio test
-
A. Wald and J. Wolfowitz, "Optimum character of the sequential probability ratio test," Ann. Math. Stat., vol.19, no.3, pp. 326-339, 1948.
-
(1948)
Ann. Math. Stat.
, vol.19
, Issue.3
, pp. 326-339
-
-
Wald, A.1
Wolfowitz, J.2
-
35
-
-
51549101059
-
Predictive dynamic thermal management for multicore systems
-
Jun
-
I. Yeo, C. C. Liu, and E. J. Kim, "Predictive dynamic thermal management for multicore systems," in Proc. DAC, Jun. 2008, pp. 734-739.
-
(2008)
Proc. DAC
, pp. 734-739
-
-
Yeo, I.1
Liu, C.C.2
Kim, E.J.3
-
36
-
-
0036056702
-
Task scheduling and voltage selection for energy minimization
-
Y. Zhang, X. S. Hu, and D. Z. Chen, "Task scheduling and voltage selection for energy minimization," in Proc. DAC, 2002, pp. 183-188.
-
(2002)
Proc. DAC
, pp. 183-188
-
-
Zhang, Y.1
Hu, X.S.2
Chen, D.Z.3
|