Proactive temperature balancing for low cost thermal management in MPSoCs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2008, Pages 250-257

  Coskun, Ayse Kivilcim ^a   Rosing, Tajana Simunic ^a   Gross, Kenny C ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADVERSE EFFECTS; DIE TEMPERATURES; HOT SPOTS; JOB ALLOCATIONS; LOW COSTS; MULTI PROCESSOR SYSTEM ON CHIPS; PERFORMANCE COSTS; PROACTIVE MANAGEMENTS; TEMPERATURE BALANCING; TEMPERATURE VARIATIONS; THERMAL MANAGEMENTS; ULTRASPARC;

COMPUTER AIDED DESIGN; TEMPERATURE CONTROL; THERMAL VARIABLES CONTROL; WIRELESS TELECOMMUNICATION SYSTEMS;

TEMPERATURE;

EID: 57849133498     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681582     Document Type: Conference Paper

References (28)

1. A. H. Ajami, K. Banerjee, and M. Pedram. Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Transactions on CAD, 24(6):849-861, June 2005.
2. D. Atienza, G. D. Micheli, L. Benini, J. L. Ayala, P. G. D. Valle, M. DeBole, and V. Narayanan. Reliability-aware design for nanometer-scale devices. In ASPDAC, 2008.
3. D. Atienza, P. D. Valle, G. Paci, F. Poletti, L. Benini, G. D. Micheli, and J. M. Mendias. A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. In DAC, 2006.
4. A. K. Coskun, T. Rosing, and K. Whisnant. Temperature aware task scheduling in MPSoCs. In DATE, 2007.
5. J. Donald and M. Martonosi. Techniques for multicore thermal management: Classification and new exploration. In ISCA, 2006.
6. M. Gomaa, M. D. Powell, and T. N. Vijaykumar. Heat-and-Run: leveraging SMT and CMP to manage power density through the operating system. In ASPLOS, 2004.
7. K. Gross, K. Whisnant, and A. Urmanov. Electronic prognostics through continuous system telemetry. In MFPT, pages 53-62, April 2006.
8. K. C. Gross and K. E. Humenik. Sequential probability ratio test for nuclear plant component surveillance. Nuclear Technology, 93(2): 131-137, Feb 1991.
9. J. Hu and R. Marculescu. Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In DATE, 2004.
10. W.-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Thermal-aware task allocation and scheduling for embedded systems. In DATE, 2005.
11. Failure mechanisms and models for semiconductor devices, JEDEC publication JEP122C. http://www.jedec.org.
12. A. Karlin, M. Manesse, L. McGeoch, and S. Owicki. Competitive randomized algorithms for nonuniform problems. Algorithmica, 1994.
13. H. Kufluoglu and M. A. Alam. A computational model of NBTI and hot carrier injection time-exponents for MOSFET reliability. Journal of Computational Electronics, 3 (3):165-169, Oct. 2004.
14. A. Kumar, L. Shang, L.-S. Peh, and N. K. Jha. HybDTM: a coordinated hardware-software approach for dynamic thermal management. In DAC, pages 548-553, 2006.
15. E. Kursun, C.-Y. Cher, A. Buyuktosunoglu, and P.Bose. Investigating the effects of task scheduling on thermal behavior. In TACS, 2006.
16. A. Leon, L. Jinuk, K. Tam, W. Bryg, F. Schumacher, P. Kongetira, D. Weisner, and A. Strong. A power-efficient high-throughput 32-thread SPARC processor. ISSCC, 2006.
17. J. Liu, P. H. Chou, N. Bagherzadeh, and F. Kurdahi. Power-aware scheduling under timing constraints for mission-critical embedded systems. In DAC, 2001.
18. R. McDougall, J. Mauro, and B. Gregg. Solaris Performance and Tools. Sun Microsystems Press, 2006.
19. P. Rong and M. Pedram. Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system. In ASPDAC, 2006.
20. T. S. Rosing, K. Mihic, and G. D. Micheli. Power and reliability management of SoCs. IEEE Transactions on VLSI, 15(4), April 2007.
21. M. Ruggiero, A. Guerri, D. Bertozzi, F. Poletti, and M. Milano. Communication-aware allocation and scheduling framework for stream-oriented multi-processor system-on-chip. In DATE, 2006.
22. K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-aware microarchitecture. In ISCA, 2003.
23. SLAMD Distributed Load Engine, www.slamd.com.
24. J. Srinivasan and S. V. Adve. Predictive dynamic thermal management for multimedia applications. In ICS, 2003.
25. J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. The case for lifetime reliability-aware microprocessors. In ISCA, 2004.
26. H. Su, F. Liu, A. Devgan, E. Acar, and S. Nassif. Full-chip leakage estimation considering power supply and temperature variations. In ISLPED, 2003.
27. A. Wald and J. Wolfowitz. Optimum character of the sequential probability ratio test. Ann. Math. Stat., 19:326, 1948.
28. Y. Zhang, X. S. Hu, and D. Z. Chen. Task scheduling and voltage selection for energy minimization. In DAC, 2002.