Vertical integration of stacked DRAM and high-speed logic device using SMAFTI technology

IEEE Transactions on Advanced Packaging

Volumn 32, Issue 3, 2009, Pages 657-665

  Kurita, Yoichiro ^a   Matsui, Satoshi ^a   Takahashi, Nobuaki ^a   Soejima, Koji ^a   Komuro, Masahiro ^a   Itou, Makoto ^a   Kawano, Masaya ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Bump interconnection; Fine interposer; Stacked memory; Three dimensional LSI; Through silicon vias (TSVs)

Indexed keywords

BUMP INTERCONNECTION; FINE INTERPOSER; STACKED MEMORY; THREE-DIMENSIONAL LSI; THROUGH-SILICON VIAS (TSVS);

DYNAMIC RANDOM ACCESS STORAGE; INTERCONNECTION NETWORKS; LOGIC CIRCUITS; LOGIC DEVICES; LSI CIRCUITS; METALLIC COMPOUNDS; MOS DEVICES; POLYSILICON; RELIABILITY ANALYSIS; THERMAL AGING; THREE DIMENSIONAL;

SEMICONDUCTING SILICON;

EID: 68949175484     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2009.2015461     Document Type: Article

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