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1
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0034835759
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Thermal characterization of bare-die stacked modules with Cu through-vias
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Orlando, FL, May/June
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th Electric Components and Technology Conference (ECTC 2001), Orlando, FL, May/June, 2001, pp. 730-737.
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(2001)
th Electric Components and Technology Conference (ECTC 2001)
, pp. 730-737
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Yamaji, Y.1
Ando, T.2
Morifuji, T.3
Tomisaka, M.4
Sunohara, M.5
Sato, T.6
Takahashi, K.7
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2
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33845567961
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A novel "SMAFTI" package for inter-chip wide-band data transfer
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San Diego, CA, May/June
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Y. Kurita, K. Soejima, K. Kikuchi, M Takahashi, M. Tago, M Koike, K. Shibuya, S. Yamamichi, and M. Kawano, "A Novel "SMAFTI" Package for Inter-Chip Wide-Band Data Transfer," Proc. of 56th Electric Components and Technology Conference (ECTC 2006), San Diego, CA, May/June, 2006, pp. 289-297.
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(2006)
Proc. of 56th Electric Components and Technology Conference (ECTC 2006)
, pp. 289-297
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Kurita, Y.1
Soejima, K.2
Kikuchi, K.3
Takahashi, M.4
Tago, M.5
Koike, M.6
Shibuya, K.7
Yamamichi, S.8
Kawano, M.9
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3
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46649112241
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Stacked memory chip technology development
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Session 9 Dec.
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H. Ikeda, M. Kawano, and T. Mitsuhashi, "Stacked Memory Chip Technology Development," SEMI Technology Symposium (STS) 2005 Proceedings, Session 9 pp. 37-42, Dec. 2005.
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(2005)
SEMI Technology Symposium (STS) 2005 Proceedings
, pp. 37-42
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Ikeda, H.1
Kawano, M.2
Mitsuhashi, T.3
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4
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46049089466
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A 3D packaging technology for 4 gbit stacked DRAM with 3 gbps data transfer
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San Francisco, CA, Dec.
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M. Kawano, S. Uchiyama, Y. Egawa, N. Takahashi, Y. Kurita, K. Soejima, M. Komuro, S. Matsui, K. Shibata, J. Yamada, M. Ishino, H. Ikeda, Y. Saeki, O. Kato, H. Kikuchi, and T. Mitsuhashi, "A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer," International Electron Devices Meeting Technical Digest (IEDM 2006), San Francisco, CA, Dec., 2006, pp. 581-584.
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(2006)
International Electron Devices Meeting Technical Digest (IEDM 2006)
, pp. 581-584
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Kawano, M.1
Uchiyama, S.2
Egawa, Y.3
Takahashi, N.4
Kurita, Y.5
Soejima, K.6
Komuro, M.7
Matsui, S.8
Shibata, K.9
Yamada, J.10
Ishino, M.11
Ikeda, H.12
Saeki, Y.13
Kato, O.14
Kikuchi, H.15
Mitsuhashi, T.16
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5
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34250860025
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Development of 3D-packaging process technology for stacked memory chips
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T. Mitsuhashi, Y. Egawa, O. Kato, Y. Saeki, H. Kikuchi, S. Uchiyama, K. Shibata, J. Yamada, M. Ishino, H. Ikeda, N. Takahashi, Y. Kurita, M. Komuro, S. Matsui, and M. Kawano, "Development of 3D-Packaging Process Technology for Stacked Memory Chips," Mater. Res. Soc. Symp. Proc., Vol. 970, 0970-Y03-06, 2007.
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(2007)
Mater. Res. Soc. Symp. Proc.
, vol.970
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Mitsuhashi, T.1
Egawa, Y.2
Kato, O.3
Saeki, Y.4
Kikuchi, H.5
Uchiyama, S.6
Shibata, K.7
Yamada, J.8
Ishino, M.9
Ikeda, H.10
Takahashi, N.11
Kurita, Y.12
Komuro, M.13
Matsui, S.14
Kawano, M.15
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6
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35348862384
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A 3D stacked memory integrated on a logic device using SMAFTI technology
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Reno, NV, May/June
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th Electric Components and Technology Conference (ECTC 2007), Reno, NV, May/June, 2007, pp. 821-829.
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(2007)
th Electric Components and Technology Conference (ECTC 2007)
, pp. 821-829
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Kurita, Y.1
Matsui, S.2
Takahashi, N.3
Soejima, K.4
Komuro, M.5
Itou, M.6
Kakegawa, C.7
Kawano, M.8
Egawa, Y.9
Saeki, Y.10
Kikuchi, H.11
Kato, O.12
Yanagisawa, A.13
Mitsuhashi, T.14
Ishino, M.15
Shibata, K.16
Uchiyama, S.17
Yamada, J.18
Ikeda, H.19
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7
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46649097143
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Development of high-density package for stacked DRAM using through-silicon vias
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Nov. To be published
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M. Kawano, N. Takahashi, Y. Kurita, K. Soejima, M. Komuro, S. Matsui, S. Uchiyama, K. Shibata, J. Yamada, M. Ishino, H. Ikeda, Y. Egawa, Y. Saeki, O. Kato, H. Kikuchi, A. Yanagisawa, and T. Mitsuhashi, "Development of High-Density Package for Stacked DRAM using Through-Silicon Vias", IEICE Transactions (C), Vol. J90-C, No.11, Nov.2007, To be published.
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(2007)
IEICE Transactions (C)
, vol.J90-C
, Issue.11
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Kawano, M.1
Takahashi, N.2
Kurita, Y.3
Soejima, K.4
Komuro, M.5
Matsui, S.6
Uchiyama, S.7
Shibata, K.8
Yamada, J.9
Ishino, M.10
Ikeda, H.11
Egawa, Y.12
Saeki, Y.13
Kato, O.14
Kikuchi, H.15
Yanagisawa, A.16
Mitsuhashi, T.17
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