Template-free symbolic performance modeling of analog circuits via canonical-form functions and genetic programming

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 8, 2009, Pages 1162-1175

  McConaghy, Trent ^a   Gielen, Georges G E ^b  

^a Solido Design Automation Inc Canada   (Canada)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Macromodeling; Performance optimization; Posynomial; Transistor sizing; Yield modeling

Indexed keywords

MACROMODELING; PERFORMANCE OPTIMIZATION; POSYNOMIAL; TRANSISTOR SIZING; YIELD MODELING;

ANALOG CIRCUITS; GENETIC PROGRAMMING;

SPICE;

EID: 68549126871     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2021034     Document Type: Article

References (51)

1. R. A. Rutenbar, G. G. E. Gielen, and J. Roychowdhury, "Hierarchical modeling, optimization, and synthesis for system-level analog and RF designs," Proc. IEEE, vol. 95, no. 3, pp. 640-669, Mar. 2007.
2. G. G. E. Gielen, "Techniques and applications of symbolic analysis for analog integrated circuits: A tutorial overview," in Computer-Aided Design of Analog Integrated Circuits and Systems, R. A. Rutenbar, G. G. E. Gielen, and B. A. Antao, Eds. New York: Wiley, 2002, pp. 245-261.
3. G. G. E. Gielen, H. Walscharts, and W. M. C. Sansen, "ISAAC: A symbolic simulator for analog integrated circuits," IEEE J. Solid-State Circuits, vol. 24, no. 6, pp. 1587-1597, Dec. 1989.
4. A. Manthe, Z. Li, and C.-J. Richard Shi, "Symbolic analysis of analog circuits with hard nonlinearity," in Proc. Des. Autom. Conf., 2003, pp. 542-545.
5. J. Yang, S. X.-D. Tan, Z. Qi, and M. Gawecki, "Hierarchical symbolic piecewise-linear circuit analysis," in Proc. Behavioral Model. Simul., 2005, pp. 140-145.
6. N. Dong and J. Roychowdhury, "General-purpose nonlinear model-order reduction using piecewise-polynomial representations," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 2, pp. 249-264, Feb. 2008.
7. P. Drennan, M. Kniffin, and D. Locascio, "Implications of proximity effects for analog design," in Proc. Custom Integr. Circuit Conf., 2006, pp. 169-176.
8. H. E. Graeb, Analog Design Centering and Sizing. Berlin, Germany: Springer-Verlag, 2007.
9. X. Li and H. Liu, "Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations," in Proc. Des. Autom. Conf., 2008, pp. 38-43.
10. W. Daems, G. G. E. Gielen, and W. M. C. Sansen, "An efficient optimization-based technique to generate posynomial performance models for analog integrated circuits," in Proc. Des. Autom. Conf., 2002, pp. 431-436.
11. W. Daems, G. G. E. Gielen, and W. M. C. Sansen, "Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 5, pp. 517-534, May 2003.
12. V. Aggarwal and U.-M. O'Reilly, "Simulation-based reusable posynomial models for MOS transistor parameters," in Proc. Des. Autom. Test Eur. Conf., 2007, pp. 69-74.
13. X. Li, P. Gopalakrishnan, Y. Xu, and L. Pileggi, "Robust analog/RF circuit design with projection-based performance modeling," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 1, pp. 2-15, Jan. 2007.
14. Z. Feng and P. Li, "Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2006, pp. 868-875.
15. G. Wolfe and R. Vemuri, "Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2004, pp. 931-938.
16. P. Vancorenland, G. Van der Plas, M. Steyaert, G. G. E. Gielen, and W. M. C. Sansen, "A layout-aware synthesis methodology for RF circuits," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., Nov. 2001, pp. 358-362.
17. G. Wolfe and R. Vemuri, "Extraction and use of neural network models in automated synthesis of operational amplifiers," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 2, pp. 198-212, Feb. 2003.
18. H. Liu, A. Singhee, R. A. Rutenbar, and L. R. Carley, "Remembrance of circuits past: Macromodeling by data mining in large analog design spaces," in Proc. Des. Autom. Conf., 2002, pp. 437-442.
19. F. De Bernardinis, M. I. Jordan, and A. L. Sangiovanni-Vincentelli, "Support vector machines for analog circuit performance representation," in Proc. Des. Autom. Conf., 2003, pp. 964-969.
20. T. Kiely and G. G. E. Gielen, "Performance modeling of analog integrated circuits using least-squares support vector machines," in Proc. Des. Autom. Test Eur. Conf., 2004, pp. 448-453.
21. M. Ding and R. Vemuri, "A two-level modeling approach to analog circuit performance macromodeling," in Proc. Des. Autom. Test Eur. Conf., 2005, pp. 1088-1089.
22. A. Singhee and R. A. Rutenbar, "Beyond low-order statistical response surfaces: Latent variable regression for efficient, highly nonlinear fitting," in Proc. Des. Autom. Conf., 2007, pp. 256-261.
23. X. Li and Y. Cao, "Projection-based piecewise-linear response surface modeling for strongly nonlinear VLSI performance variations," in Proc. Int. Symp. Quality Electron. Des., 2008, pp. 108-113.
24. G. Yu and P. Li, "Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2007, pp. 464-469.
25. T. McConaghy and G. G. E. Gielen, "Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization," in Proc. Int. Symp. Circuits Syst., May 2005, pp. 1298-1301.
26. T. McConaghy, P. Palmers, G. G. E. Gielen, and M. Steyaert, "Automated extraction of expert knowledge in analog topology selection and sizing," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., San Jose, CA, Nov. 2008, pp. 392-395.
27. T. McConaghy, T. Eeckelaert, and G. G. E. Gielen, "CAFFEINE: Template-free symbolic model generation of analog circuits via canonical form functions and genetic programming," in Proc. Des. Autom. Test Eur. Conf., Mar. 2005, pp. 243-246.
28. J. R. Koza, Genetic Programming. Cambridge, MA: MIT Press, 1992.
29. P. A. Whigham, "Grammatically-based genetic programming," in Proc. Workshop Genetic Program., J. R. Rosca, Ed., 1995, pp. 33-41.
30. K. Deb, S. Agrawal, A. Pratap, and T. Meyarivan, "A fast and elitist multiobjective genetic algorithm: NSGA-II," IEEE Trans. Evol. Comput., vol. 6, no. 2, pp. 182-197, Apr. 2002.
31. M. O'Neill and C. Ryan, Grammatical Evolution: Evolutionary Automatic Programming in an Arbitrary Language. Norwell, MA: Kluwer, 2003.
32. M. Keijzer, "Alternatives in subtree caching for genetic programming," in Proc. Eur. Conf. Genetic Program., 2004, pp. 328-337.
33. J. H. Friedman and B. E. Popescu, "Gradient directed regularization for linear regression and classification," Dept. Stat., Stanford Univ., Stanford, CA, Feb. 2004. Tech. Rep.
34. D. C. Montgomery, Design and Analysis of Experiments, 6th ed. New York: Wiley, 2004.
35. T. Soule and R. B. Heckendom, "An analysis of the causes of code growth in genetic programming," Genet. Program. Evolvable Mach., vol. 3, no. 3, pp. 283-309, Sep. 2002.
36. E. Kirshenbaum and H. J. Suermondt, "Using genetic programming to obtain a closed-form approximation to a recursive function," in Proc. Genetic Evol. Comput. Conf., 2005, pp. 543-556.
37. P. Wambacq, F. V. Fernandez, G. Gielen, W. Sansen, and A. Rodriguez-Vazquez, "Efficient symbolic computation of approximate small-signal characteristics," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 327-330, Mar. 1995.
38. X. Yao, Y. Liu, and G. Lin, "Evolutionary programming made faster," IEEE Trans. Evol. Comput., vol. 3, no. 2, pp. 82-102, Jul. 1999.
39. F. Leyn, G. G. E. Gielen, and W. M. C. Sansen, "An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 1998, pp. 304-307.
40. N. Ampazis and S. J. Perantonis, "Two highly efficient second order algorithms for training feedforward networks," IEEE Trans. Neural Netw., vol. 13, no. 5, pp. 1064-1074, Sep. 2002.
41. J. H. Friedman, "Multivariate adaptive regression splines," Ann. Stat., vol. 19, no. 1, pp. 1-67, Mar. 1991.
42. J. A. K. Suykens and J. Vandewalle, Least Squares Support Vector Machines. Singapore: World Scientific, 2002.
43. D. R. Jones, M. Schonlau, and W. J. Welch, "Efficient global optimization of expensive black-box functions," J. Glob. Optim., vol. 13, no. 4, pp. 455-492, Dec. 1998.
44. A. E. Horel and R. W. Kennard, "Ridge regression: Biased estimation for nonorthogonal problems," Technometrics, vol. 12, no. 1, pp. 56-67, Feb. 1970.
45. R. Tibshirani, "Regression shrinkage and selection via the lasso," J. R. Stat. Soc. B, vol. 58, no. 1, pp. 267-288, 1997.
46. "LAPACK": Linear Algebra PACKage, Dec. 22, 2008. [Online]. Available: http://netlib.org/lapack
47. J. H. Friedman and B. E. Popescu, "Predictive learning via rule ensembles," Dept. Stat., Stanford Univ., Stanford, CA, Feb. 2005. Tech. Rep.
48. M. D. McKay, W. J. Conover, and R. J. Beckman, "A comparison of three methods for selecting values of input variables in the analysis of output from a computer code," Technometrics, vol. 21, no. 2, pp. 239-245, 1979.
49. "What is process capability?" NIST/SEMATECH e-Handbook of Statistical Methods, Nat. Inst. Standards Technol., Gaithersburg, MD, Dec. 22, 2008, sec. 6.1.6. [Online]. Available: http://www.itl.nist.gov/ div898/handbook/pmc/section1/pmc16.htm
50. T. McConaghy and G. G. E. Gielen, "Automation in mixed-signal design: Challenges and solutions in the wake of the nano era," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2006, pp. 461-463.
51. T. McConaghy and G. G. E. Gielen, "IBMG: Interpretable behavioral model generator for nonlinear analog circuits via canonical form functions and genetic programming," in Proc. Int. Symp. Circuits Syst., 2005, pp. 5170-5173.