-
1
-
-
0000195442
-
Computer-aided design of analog and mixed-signal integrated circuits
-
Dec
-
G. Gielen and R. Rutenbar, "Computer-aided design of analog and mixed-signal integrated circuits," Proc. IEEE, vol. 88, no. 12, pp. 1825-1852, Dec. 2000.
-
(2000)
Proc. IEEE
, vol.88
, Issue.12
, pp. 1825-1852
-
-
Gielen, G.1
Rutenbar, R.2
-
2
-
-
0023994941
-
DELIGHT. SPICE: An optimization-based system for the design of integrated circuits
-
Apr
-
W. Nye, D. Riley, A. Sangiovanni-Vincentelli, and A. Tits, "DELIGHT. SPICE: An optimization-based system for the design of integrated circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 7, no. 4, pp. 501-519, Apr. 1988.
-
(1988)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
, vol.7
, Issue.4
, pp. 501-519
-
-
Nye, W.1
Riley, D.2
Sangiovanni-Vincentelli, A.3
Tits, A.4
-
3
-
-
0032639484
-
MAELSTROM: Efficient simulation-based synthesis for custom analog cells
-
M. Krasnicki, R. Phelps, R. Rutenbar, and L. Carley, "MAELSTROM: Efficient simulation-based synthesis for custom analog cells," in Proc. IEEE/ACM Des. Autom. Conf., 1999, pp. 945-950.
-
(1999)
Proc. IEEE/ACM Des. Autom. Conf
, pp. 945-950
-
-
Krasnicki, M.1
Phelps, R.2
Rutenbar, R.3
Carley, L.4
-
4
-
-
0033702867
-
Anaconda: Simulation-based synthesis of analog circuits via stochastic pattern search
-
Jun
-
R. Phelps, M. Krasnicki, R. Rutenbar, L. Carley, and J. Hellums, "Anaconda: Simulation-based synthesis of analog circuits via stochastic pattern search," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 6, pp. 703-717, Jun. 2000.
-
(2000)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
, vol.19
, Issue.6
, pp. 703-717
-
-
Phelps, R.1
Krasnicki, M.2
Rutenbar, R.3
Carley, L.4
Hellums, J.5
-
5
-
-
0035208991
-
ASP: A practical simulation-based methodology for the synthesis of custom analog circuits
-
M. Krasnicki, R. Phelps, J. Hellums, M. McClung, R. Rutenbar, and L. Carley, "ASP: A practical simulation-based methodology for the synthesis of custom analog circuits," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2001, pp. 350-357.
-
(2001)
Proc. IEEE/ACM Int. Conf. Comput.-Aided Des
, pp. 350-357
-
-
Krasnicki, M.1
Phelps, R.2
Hellums, J.3
McClung, M.4
Rutenbar, R.5
Carley, L.6
-
6
-
-
0035440922
-
AMGIE - A synthesis environment for CMOS analog integrated circuits
-
Sep
-
G. Plas, G. Debyser, F. Leyn, K. Lampaert, J. Vandenbussche, G. Gielen, W. Sansen, P. Veselinovic, and D. Leenaerts, "AMGIE - A synthesis environment for CMOS analog integrated circuits," IEEE Trans. Comput.Aided Design Integr. Circuits Syst., vol. 20, no. 9, pp. 1037-1058, Sep. 2001.
-
(2001)
IEEE Trans. Comput.Aided Design Integr. Circuits Syst
, vol.20
, Issue.9
, pp. 1037-1058
-
-
Plas, G.1
Debyser, G.2
Leyn, F.3
Lampaert, K.4
Vandenbussche, J.5
Gielen, G.6
Sansen, W.7
Veselinovic, P.8
Leenaerts, D.9
-
7
-
-
0043094101
-
A high-level simulation and synthesis environment for AS modulators
-
Aug
-
K. Francken and G. Gielen, "A high-level simulation and synthesis environment for AS modulators," IEEE Trans. Comput. -Aided Design Integr. Circuits Syst., vol. 22, no. 8, pp. 1049-1061, Aug. 2003.
-
(2003)
IEEE Trans. Comput. -Aided Design Integr. Circuits Syst
, vol.22
, Issue.8
, pp. 1049-1061
-
-
Francken, K.1
Gielen, G.2
-
8
-
-
0032683657
-
Optimization of inductor circuits via geometric programming
-
M. Hershenson, S. Mohan, S. Boyd, and T. Lee, "Optimization of inductor circuits via geometric programming," in Proc. IEEE/ACM Des. Autom. Conf., 1999, pp. 994-998.
-
(1999)
Proc. IEEE/ACM Des. Autom. Conf
, pp. 994-998
-
-
Hershenson, M.1
Mohan, S.2
Boyd, S.3
Lee, T.4
-
9
-
-
0033353050
-
Design and optimization of LC oscillators
-
M. Hershenson, A. Hajimiri, S. Mohan, S. Boyd, and T. Lee, "Design and optimization of LC oscillators," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 1999, pp. 65-69.
-
(1999)
Proc. IEEE/ACM Int. Conf. Comput.-Aided Des
, pp. 65-69
-
-
Hershenson, M.1
Hajimiri, A.2
Mohan, S.3
Boyd, S.4
Lee, T.5
-
10
-
-
0035059137
-
Optimal design of a CMOS Op-Amp via geometric programming
-
Jan
-
M. Hershenson, S. Boyd, and T. Lee, "Optimal design of a CMOS Op-Amp via geometric programming," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 1, pp. 1-21, Jan. 2001.
-
(2001)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
, vol.20
, Issue.1
, pp. 1-21
-
-
Hershenson, M.1
Boyd, S.2
Lee, T.3
-
12
-
-
0027557081
-
Statistical integrated circuit design
-
Mar
-
S. Director, P. Feldmann, and K. Krishna, "Statistical integrated circuit design," IEEE J. Solid-State Circuits, vol. 28, no. 3, pp. 193-202, Mar. 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, Issue.3
, pp. 193-202
-
-
Director, S.1
Feldmann, P.2
Krishna, K.3
-
13
-
-
0027969744
-
An efficient yield optimization method using a two step linear approximation of circuit performance
-
Z. Wang and S. Director, "An efficient yield optimization method using a two step linear approximation of circuit performance," in Proc. IEEE Eur. Des. Test Conf., 1994, pp. 567-571.
-
(1994)
Proc. IEEE Eur. Des. Test Conf
, pp. 567-571
-
-
Wang, Z.1
Director, S.2
-
14
-
-
0034846245
-
Mismatch analysis and direct yield optimization by specwise linearization and feasibility-guided search
-
F. Schenkel, M. Pronath, S. Zizala, R. Schwencker, H. Graeb, and K. Antreich, "Mismatch analysis and direct yield optimization by specwise linearization and feasibility-guided search," in Proc. IEEE/ACM Des. Autom. Conf., 2001, pp. 858-863.
-
(2001)
Proc. IEEE/ACM Des. Autom. Conf
, pp. 858-863
-
-
Schenkel, F.1
Pronath, M.2
Zizala, S.3
Schwencker, R.4
Graeb, H.5
Antreich, K.6
-
15
-
-
0028256775
-
Circuit analysis and optimization driven by worst-case distances
-
Jan
-
K. Antreich, H. Graeb, and C. Wieser, "Circuit analysis and optimization driven by worst-case distances," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 13, no. 1, pp. 57-71, Jan. 1994.
-
(1994)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
, vol.13
, Issue.1
, pp. 57-71
-
-
Antreich, K.1
Graeb, H.2
Wieser, C.3
-
16
-
-
0032763043
-
A unified approach to statistical design centering of integrated circuits with correlated parameters, IEEE Trans. Circuits Syst. I
-
Jan
-
A. Seifi, K. Ponnambalam, and J. Vlach, "A unified approach to statistical design centering of integrated circuits with correlated parameters," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 46, no. 1, pp. 190-196, Jan. 1999.
-
(1999)
Fundam. Theory Appl
, vol.46
, Issue.1
, pp. 190-196
-
-
Seifi, A.1
Ponnambalam, K.2
Vlach, J.3
-
17
-
-
0029289926
-
Worst-case analysis and optimization of VLSI circuit performances
-
Apr
-
A. Dharchoudhury and S. Kang, "Worst-case analysis and optimization of VLSI circuit performances," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 14, no. 4, pp. 481-492, Apr. 1995.
-
(1995)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
, vol.14
, Issue.4
, pp. 481-492
-
-
Dharchoudhury, A.1
Kang, S.2
-
18
-
-
0032319738
-
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
-
G. Debyser and G. Gielen, "Efficient analog circuit synthesis with simultaneous yield and robustness optimization," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 1998, pp. 308-311.
-
(1998)
Proc. IEEE/ACM Int. Conf. Comput.-Aided Des
, pp. 308-311
-
-
Debyser, G.1
Gielen, G.2
-
19
-
-
0034248778
-
Efficient handling of operating range and manufacturing line variations in analog cell synthesis
-
Aug
-
T. Mukherjee, L. Carley, and R. Rutenbar, "Efficient handling of operating range and manufacturing line variations in analog cell synthesis," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 8, pp. 825-839, Aug. 2000.
-
(2000)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
, vol.19
, Issue.8
, pp. 825-839
-
-
Mukherjee, T.1
Carley, L.2
Rutenbar, R.3
-
22
-
-
0035209035
-
Simulation-based automatic generation of signomial and posynomial performance models for analog integrated circuit sizing
-
W. Daems, G. Gielen, and W. Sansen, "Simulation-based automatic generation of signomial and posynomial performance models for analog integrated circuit sizing," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2001, pp. 70-74.
-
(2001)
Proc. IEEE/ACM Int. Conf. Comput.-Aided Des
, pp. 70-74
-
-
Daems, W.1
Gielen, G.2
Sansen, W.3
-
23
-
-
2342658458
-
A fitting approach to generate symbolic expressions for linear and nonlinear analog circuit performance characteristics
-
_, "A fitting approach to generate symbolic expressions for linear and nonlinear analog circuit performance characteristics," in Proc. IEEE/ACM Des., Autom. Test Eur., 2002, pp. 268-273.
-
(2002)
Proc. IEEE/ACM Des., Autom. Test Eur
, pp. 268-273
-
-
Daems, W.1
Gielen, G.2
Sansen, W.3
-
24
-
-
0036044208
-
An efficient optimization-based technique to generate posynomial performance models for analog integrated circuits
-
_, "An efficient optimization-based technique to generate posynomial performance models for analog integrated circuits," in Proc. IEEE/ACM Des. Autom. Conf., 2002, pp. 431-436.
-
(2002)
Proc. IEEE/ACM Des. Autom. Conf
, pp. 431-436
-
-
Daems, W.1
Gielen, G.2
Sansen, W.3
-
25
-
-
16244399329
-
Generalized posynomial performance modeling
-
T. Eeckelaert, W. Daems, G. Gielen, and W. Sansen, "Generalized posynomial performance modeling," in Proc. IEEE/ACM Des., Autom. Test Eur., 2003, pp. 250-255.
-
(2003)
Proc. IEEE/ACM Des., Autom. Test Eur
, pp. 250-255
-
-
Eeckelaert, T.1
Daems, W.2
Gielen, G.3
Sansen, W.4
-
26
-
-
0004236492
-
-
Baltimore, MD: Johns Hopkins Univ. Press
-
G. Golub and C. Loan, Matrix Computations. Baltimore, MD: Johns Hopkins Univ. Press, 1996.
-
(1996)
Matrix Computations
-
-
Golub, G.1
Loan, C.2
-
28
-
-
0035208990
-
The sizing rules method for analog integrated circuit design
-
H. Graeb, S. Zizala, J. Eckmueller, and K. Antreich, "The sizing rules method for analog integrated circuit design," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2001, pp. 343-349.
-
(2001)
Proc. IEEE/ACM Int. Conf. Comput.-Aided Des
, pp. 343-349
-
-
Graeb, H.1
Zizala, S.2
Eckmueller, J.3
Antreich, K.4
-
29
-
-
0346148467
-
Initial sizing of analog integrated circuits by centering within topology-given implicit specifications
-
G. Stehr, M. Pronath, F. Schenkel, H. Graeb, and K. Antreich, "Initial sizing of analog integrated circuits by centering within topology-given implicit specifications," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2003, pp. 241-246.
-
(2003)
Proc. IEEE/ACM Int. Conf. Comput.-Aided Des
, pp. 241-246
-
-
Stehr, G.1
Pronath, M.2
Schenkel, F.3
Graeb, H.4
Antreich, K.5
-
30
-
-
16244393708
-
Asymptotic probability extraction for non-Normal distributions of circuit performance
-
X. Li, J. Le, P. Gopalakrishnan, and L. Pileggi, "Asymptotic probability extraction for non-Normal distributions of circuit performance," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2004, pp. 2-9.
-
(2004)
Proc. IEEE/ACM Int. Conf. Comput.-Aided Des
, pp. 2-9
-
-
Li, X.1
Le, J.2
Gopalakrishnan, P.3
Pileggi, L.4
-
31
-
-
33751436870
-
Projection-based performance modeling for inter/intra-die variations
-
X. Li, J. Le, L. Pileggi, and A. Strojwas, "Projection-based performance modeling for inter/intra-die variations," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2005, pp. 721-727.
-
(2005)
Proc. IEEE/ACM Int. Conf. Comput.-Aided Des
, pp. 721-727
-
-
Li, X.1
Le, J.2
Pileggi, L.3
Strojwas, A.4
-
34
-
-
0024931842
-
An efficient methodology for building macro-models of IC fabrication processes
-
Dec
-
K. Low and S. Director, "An efficient methodology for building macro-models of IC fabrication processes," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 8, no. 12, pp. 1299-1313, Dec. 1989.
-
(1989)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
, vol.8
, Issue.12
, pp. 1299-1313
-
-
Low, K.1
Director, S.2
|