Stress controlled shallow trench isolation technology to suppress the novel anti-isotropic impurity diffusion for 45nm-node high-performance CMOSFETs

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 138-139

  Ota, K ^a   Yokoyama, T ^a   Kawasaki, H ^b   Moriya, M ^a   Kanal, T ^a   Takahashi, S ^a   Sanuki, T ^b   Hasumi, E ^b   Komoguchi, T ^a   Sogo, Y ^a   Takasu, Y ^b   Eda, K ^b   Oishi, A ^b   Kasai, K ^b   Ohno, K ^a   Iwai, M ^b   Saito, M ^a   Matsuoka, F ^b   Nagashima, N ^a   Noguchi, T ^b   Okamoto, Y ^a   more..

^a SONY CORPORATION   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; DIFFUSION; IMPURITIES; OPTIMIZATION;

ANTI-ISOTROPIC IMPURITY DIFFUSION; SHALLOW TRENCH ISOLATION TECHNOLOGY; SOC PLATFORM; STI FILLING;

MOSFET DEVICES;

EID: 33745161510     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469243     Document Type: Conference Paper

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