Implementation of SOG devices with embedded through-wafer silicon vias using a glass reflow process for wafer-level 3D MEMS integration

Proceedings of the IEEE International Conference on Micro Electro Mechanical Systems (MEMS)

Volumn , Issue , 2008, Pages 802-805

  Lin, Chiung Wen ^a   Hsu, Chia Pao ^a   Yang, Hsueh An ^b   Wei, Chung Wang ^a,b   Fang, Weileun ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b ADVANCED SEMICONDUCTOR ENGINEERING INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC COMPOUNDS; CHIP SCALE PACKAGES; CHLORINE COMPOUNDS; COMPOSITE MICROMECHANICS; ELECTRONIC EQUIPMENT MANUFACTURE; GLASS; HELIUM; INERT GASES; INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; MECHANICAL ENGINEERING; MECHANICS; MECHATRONICS; MEMS; MICROELECTROMECHANICAL DEVICES; MICROMACHINING; MICROSYSTEMS; NONMETALS; PHOTOMASKS; PHOTORESISTS; REACTIVE ION ETCHING; SILICON; SILICON COMPOUNDS; SILICON WAFERS; SURFACE MOUNT TECHNOLOGY; THERMAL EXPANSION; THERMAL SPRAYING; WAFER BONDING;

3-D MEMS; ANODIC BONDING; COEFFICIENT OF THERMAL EXPANSION; COMPOUND SUBSTRATE; HELIUM LEAK TESTING; HERMETICITY; INTERNATIONAL CONFERENCES; MEMS DEVICES; MICRO-ELECTRO MECHANICAL SYSTEMS; PACKAGING DEVICES; PARASITIC CAPACITANCES; PYREX GLASS; REFLOW PROCESS; SILICON VIAS; SILICON-ON-GLASS; SYSTEM ARCHITECTURES; WAFER LEVELS; WAFER-LEVEL HERMETIC PACKAGING;

ELECTRONICS PACKAGING;

EID: 50149117013     PISSN: 10846999     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMSYS.2008.4443778     Document Type: Conference Paper

References (11)

1. V. Kaajakari, J. Kiihamaki, A. Oja, H. Seppa, S. Pietikainen, V. Kokkala, and H. Kuisma, "Stability of resonators," Transducers'05, Seoul, Korea, June 5-9, 2005, pp. 916-919.
2. R.A.M. Receveur, M. Zickar, C. Marxer, V. Larik, and N.F. de Rooij, "Wafer level hermetic package and device testing of a SOI-MEMS switch for biomedical applications," J. Micromech. and Microeng., Vol. 16, pp. 676-683, 2006.
3. C.-W. Lin, H.-A. Yang, W. C. Wang, and W. Fang, "Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections," J. Micromech. and Microeng., Vol. 17, pp. 1200-1205, 2007.
4. S.-H. Lee, S. W. Lee, and K. Najafi, "A generic enviornment- resistant packaging technology for MEMS," Transducers'07, Lyon, France, June 10-14, 2007, pp. 335-338.
5. J. Wei, M. V. Velden, and P. M. Sarro, "Fabrication of vertical electrodes on chemical sidewall for picoliter liquid measurement," Transducers'07. Lyon, France, June 10-14, 2007, pp. 1612-1616.
6. T. Bauer, "High Density Through Wafer Via Technology," NSTI-Nanotech 2007, Santa Clara, California, U.S.A., May 20-24, 2007, pp. 116-119.
7. P. Merz, H.J. Quenzer, H. Bernt, B. Wagner, and M. Zoberbier, "A novel micromachining technology for structuring borosilicate glass substrates," Transducers'03, Boston, U.S.A., June 8-12, 2003, pp. 258-261.
8. "Electrical feedthroughs Using Wafer-Level Glass-Flow Technology," Achievements and Results Annual Report 2005, Fraunhofer ISIT, Itzehoe (DE), 2005
9. S.E. Alper, and T. Akin, "A Single-Crystal Silicon Symmetrical and Decoupled MEMS Gyroscopes on an Insulating Substrate," J. Microelectromech. Syst., vol. 14, pp. 707-717, 2005.
10. M. C. Lee, S. J. Kang, K. D. Jung, S.-H. Choa, and Y. C. Cho, "A high yield rate MEMS gyroscope with a packaged SiOG process," J. Micromech. and Microeng., Vol. 15, pp. 2003-2012, 2005.
11. MIL-STD-883E, US department of defense, Dec. 31, 1996.