Optimization on MOS-triggered SCR structures for On-Chip ESD protection

IEEE Transactions on Electron Devices

Volumn 56, Issue 7, 2009, Pages 1466-1472

  Chen, Shih Hung ^a,b   Ker, Ming Dou ^a,c  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^c I SHOU UNIVERSITY   (Taiwan)

Author keywords

Electrostatic discharge (ESD); ESD protection; Silicon controlled rectifiers (SCRs)

Indexed keywords

ADVANCED CMOS; CHANNEL LENGTH; CURRENT DISTRIBUTION; ELECTROSTATIC DISCHARGE (ESD); ELECTROSTATIC DISCHARGE PROTECTION; ESD PROTECTION; ESD ROBUSTNESS; HOLDING VOLTAGE; MOS TRANSISTORS; ON CHIPS; ON-CHIP ESD PROTECTION; ON-RESISTANCE; SECOND BREAKDOWN; SILICON CONTROLLED RECTIFIER; SILICON-CONTROLLED RECTIFIERS (SCRS); SUBMICROMETER CMOS; TRIGGER MECHANISM; TRIGGER VOLTAGE;

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC RECTIFIERS; ELECTROSTATIC DISCHARGE; MOS DEVICES; SEMICONDUCTING SILICON; THYRISTORS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

ELECTROSTATIC DEVICES;

EID: 67650125208     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2021359     Document Type: Article

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