Holding voltage investigation of advanced SCR-based protection structures for CMOS technology

Microelectronics Reliability

Volumn 47, Issue 9-11 SPEC. ISS., 2007, Pages 1444-1449

  Tazzoli, A ^a   Marino, F A ^a   Cordoni, M ^b   Benvenuti, A ^b   Colombo, P ^b   Zanoni, E ^a   Meneghesso, G ^a  

^a UNIVERSITY OF PADOVA   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; ELECTRIC POTENTIAL; ELECTROSTATIC DISCHARGE; GAIN CONTROL; THYRISTORS;

PARASITIC TRANSISTORS; PROCESS PARAMETERS; SELF HEATING EFFECTS; TEMPERATURE DEPENDENCE;

CMOS INTEGRATED CIRCUITS;

EID: 34548674694     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2007.07.078     Document Type: Article

References (6)

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2. Amerasekera A., and Duvvury C. ESD in silicon integrated circuits. 2nd ed. (2002), John WILEY and Sons
3. Concannon A, Vashchenko VA, Beek MT, Hopper P. A device level negative feedback in the emitter line of SCR structures as a method to realize latch-up free ESD protection. In: Proceeding of international reliability and physics symposium, IRPS 2003; p. 105-11.
4. Synopsys, TCAD tools, http://www.synopsys.com/.
5. Esmark K., Gossner H., and Standler W. Advanced simulation methods for ESD protection development. 2nd ed. (2002), John WILEY and Sons
6. Sze S.M., and Ng K.K. Physics of semiconductor devices. 3rd ed. (2007), John WILEY and Sons