Adaptive set pinning: Managing shared caches in Chip Multiprocessors

ACM SIGPLAN Notices

Volumn 43, Issue 3, 2008, Pages 135-144

  Srikantaiah, Shekhar ^a   Kandemir, Mahmut ^a   Irwin, Mary Jane ^a  

^a The Center for Nanotechnology Education and Utilization   (United States)

Author keywords

CMP; Inter processor; Intraprocessor; Set pinning; Shared cache

Indexed keywords

CMP; INTER-PROCESSOR; INTRAPROCESSOR; SET PINNING; SHARED CACHE;

BUFFER STORAGE; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; PLANNING; RESOURCE ALLOCATION; SYSTEMS ANALYSIS;

COMPUTER ARCHITECTURE;

EID: 67650085342     PISSN: 15232867     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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