Modeling cache sharing on chip multiprocessor architectures

Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC - 2006

Volumn , Issue , 2006, Pages 160-171

  Petoumenos, Pavios ^a   Keramidas, Georgios ^a   Zeffer, Håkan ^b   Kaxiras, Stefanos ^a   Hagersten, Erik ^b  

^a UNIVERSITY OF PATRAS   (Greece)

^b UPPSALA UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; INTEGRATED CIRCUITS; NANOTECHNOLOGY; QUALITY OF SERVICE;

CACHE BEHAVIORS; CACHE PARTITIONING; CACHE SHARING; DISTANCE INFORMATIONS; EXTERNAL-; GAME CONSOLES; MEMORY ACCESSES; ON CHIPS; REPLACEMENT POLICIES; RUN TIMES; SHARED CACHES; STATISTICAL MODELS; TIME INFORMATIONS;

DECAY (ORGANIC);

EID: 48449102571     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IISWC.2006.302740     Document Type: Conference Paper

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