On concurrent error detection with bounded latency in FSMs

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 596-601

  Almukhaizim, Sobeeh ^a   Drineas, Petros ^b   Makris, Yiorgos ^a  

^a Yale University   (United States)

^b RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDED LATENCY; CONCURRENT ERROR DETECTION (CED); FINITE STATE MECHANICS (FSM); RANDOMIZED ROUNDING; CONCURRENT ERROR DETECTION; DETECTION CAPABILITY; HARDWARE COST; INTEGER PROGRAM; LINEAR PROGRAMS; MINIMIZING THE NUMBER OF;

ALGORITHMS; BENCHMARKING; CODES (SYMBOLS); ERROR DETECTION; LINEAR PROGRAMMING; MATHEMATICAL MODELS; OPTIMIZATION; PARAMETER ESTIMATION; PROBLEM SOLVING; RANDOM PROCESSES; RELAXATION PROCESSES; SEQUENTIAL CIRCUITS; EXHIBITIONS; INTEGER PROGRAMMING;

COMBINATORIAL CIRCUITS; COST REDUCTION;

EID: 3042653212     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268910     Document Type: Conference Paper

References (19)

1. M. Gossel and S. Graf, Error Detection Circuits, McGraw-Hill, 1993.
2. S. J. Piestrak, "Self-checking design in Eastern Europe," IEEE Design and Test of Computers, vol. 13, no. 1, pp. 16-25, 1996.
3. S. Mitra and E. J. McCluskey, "Which concurrent error detection scheme to choose?," in International Test Conference, 2000, pp. 985-994.
4. G. Aksenova and E. Sogomonyan, "Design of self-checking built-in check circuits for automata with memory," Automation and Remote Control, vol. 36, no. 7, pp. 1169-1177, 1975.
5. S. Dhawan and R. C. De Vries, "Design of self-checking sequential machines," IEEE Transactions on Computers, vol. 37, no. 10, pp. 1280-1284, 1988.
6. N. A. Touba and E. J. McCluskey, "Logic synthesis of multilevel circuits with concurrent error detection," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 7, pp. 783-789, 1997.
7. V. V. Danilov, N. V. Kolesov, and B. P. Podkopaev, "An algebraic model for the hardware monitoring of automata," Automation and. Remote Control, vol. 36, no. 6, pp 98, 4-991, 1975.
8. C. Bolchini, F. Salice, and D. Sciuto, "A novel methodology for designing, TSC networks basad on the parity bit code" in European Design and Test Conference, 1997, pp. 440-444.
9. R. Leveugle and G. Saucier, "Optimized synthesis, of concurrently checked controllers," IEEE Transaction on Computers, vol. 39; no. 4, pp. 419-425, 1990.
10. S. H. Robinson and J. P. Shen, "Direct methods for synthesis of self-monitoring state machines," in Fault Tolerant Computing Symposium, 1992, pp. 306-315.
11. P. Drineas and Y. Makris, "SPaRe: selective partial replication for concurrent fault detection in FSMs," in International Conference on VLSI Design, 2003.
12. J. F. Meyer and R. J. Sundstrom, "On-line diagnosis of unrestricted faults," IEEE Transactions on Computers, vol. 24, no. 5, pp. 468-475, 1975.
13. E. S. Sogomonyan, "The design of discrete devices with diagnostics in the course of operation," Automation and Remote Control, vol. 31, no. 11, pp. 1854-1860, 1970.
14. L. P. Holmquist and L. L. Kinney, "Concurrent error detection for restricted fault sets in sequential circuits and micro-programmed control units using convolutional codes," in International Test Conference, 1991, pp. 926-935.
15. M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman, 1979.
16. C. Zeng, N. Saxena, and E. J. McCluskey, "Finite state machine synthesis with concurrent error detection," in International Test Conference, 1999, pp. 672-679.
17. P. Drineas and Y. Makris, "Non-intrusive concurrent error detection in FSMs through State/Output compaction and monitoring via parity trees," in Design Automation and Test in Europe Conference, 2003, pp. 1164-1165.
18. P. Raghavan and C. Thompson, "Randomized rounding: A technique for provably good algorithms and algorithmic proofs," Combinatorics, vol. 7, no. 4, pp. 365-374, 1987.
19. E. M. Sentovich et al., "SIS: a system for sequential circuit synthesis," ERL MEMO. No. UCB/ERL M92/41, EECS UC Berkeley CA 94720, 1992.