Investigation of low-frequency noise in silicon nanowire MOSFETs in the subthreshold region

IEEE Electron Device Letters

Volumn 30, Issue 6, 2009, Pages 668-671

  Wei, Chengqing ^a,b,c   Xiong, Yong Zhong ^b   Zhou, Xing ^a   Singh, Navab ^b   Rustagi, Subhash C ^b   Lo, Guo Qiang ^b   Kwong, Dim Lee ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

^c CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

Author keywords

Gate all around (GAA); Low frequency (1 f) noise; Silicon nanowire; Volume inversion

Indexed keywords

FLUCTUATION MODEL; GATE-ALL-AROUND; GATE-ALL-AROUND (GAA); HOOGE PARAMETERS; LOW-FREQUENCY (1/F) NOISE; LOW-FREQUENCY NOISE; MOBILITY ENHANCEMENT; P-TYPE; SILICON NANOWIRE; SILICON NANOWIRE MOSFETS; SILICON NANOWIRE TRANSISTORS; SUBTHRESHOLD REGION; VOLUME INVERSION;

DRAIN CURRENT; GALLIUM ALLOYS; NANOWIRES; SEMICONDUCTING ALUMINUM COMPOUNDS; SEMICONDUCTING SILICON COMPOUNDS; THERMAL NOISE;

MOSFET DEVICES;

EID: 67649410173     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2019975     Document Type: Article

References (21)

1. F. L. Yang, D. H. Lee, H. Y. Chen, C. Y. Chang, and S. D. Liu, "5 nm-gate nanowire FinFET," in VLSI Symp. Tech. Dig., 2004, pp. 196-197.
2. S. D. Suk, S. Y. Lee, S. M. Kim, E. J. Yoon, M. S. Kim, M. Li, C.W. Oh, K. H. Yeo, and S. H. Kim, "High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability," in IEDM Tech. Dig., 2005, pp. 717-720.
3. N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, and G. Q. Lo, "High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices," IEEE Electron Device Lett., vol. 27, no. 5, pp. 383-386, May 2006.
4. N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal, and C. H. Tung, "Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance," in IEDM Tech. Dig., 2006, pp. 1-4.
5. S. C. Rustagi, N. Singh, W. W. Fang, K. D. Buddharaju, S. R. Omampuliyur, and S. H. Teo, "CMOS inverter based on gate-all-around silicon-nanowire MOSFETs fabricated using top-down approach," IEEE Electron Device Lett., vol. 28, no. 11, pp. 1021-1024, Nov. 2007.
6. K. D. Buddharaju, N. Singh, S. C. Rustagi, S. H. G. Teo, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, "Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach," Solid State Electron., vol. 52, no. 9, pp. 1312-1317, Sep. 2008.
7. K. von Arnim, E. Augendre, C. Pacha, T. Schulz, K. T. San, F. Bauer, and A. Nackaerts, "A low-power multi-gate FET CMOS technology with 13.9 ps inverter delay, large-scale integrated high performance digital circuits and SRAM," in VLSI Symp. Tech. Dig., 2007, pp. 106-107.
8. N. Singh, K. D. Buddharaju, S. K. Manhas, A. Agarwal, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "Si, SiGe nanowire devices by top-down technology and their applications," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3107-3118, Nov. 2008.
9. G. J. Zhang, A. Agarwal, D. Buddharaju, N. Singh, and Z. Gao, "Highly sensitive sensors for alkali metal ions based on complementary-metal-oxide-semiconductor-compatible silicon nanowire," Appl. Phys. Lett., vol. 90, no. 23, p. 233 903, Jun. 2007.
10. G. J. Zhang, G. Zhang, J. H. Chua, R. E. Chee, E. H. Wong, A. Agarwal, and K. D. Buddharaju, "DNA sensing by silicon nanowire: Charge layer distance dependence," Nano Lett., vol. 8, no. 4, pp. 1066-1070, Apr. 2008.
11. E. Stern, J. F. Klemic, D. A. Routenberg, P. N. Wyrembak, and D. B. Turner-Evans, "Label-free immunodetection with CMOS-compatible semiconducting nanowires," Nature, vol. 445, no. 7127, pp. 519-522, Feb. 2007.
12. Y. F. Lim, Y. Z. Xiong, N. Singh, R. Yang, and Y. Jiang, "Random telegraph signal noise in gate-all-around Si-FinFET with ultra-narrow body," IEEE Electron Device Lett., vol. 27, no. 9, pp. 765-768, Sep. 2006.
13. Z. Jing, R. Wang, R. Huang, Y. Tian, L. Zhang, D. W. Kim, D. Park, and Y. Wang, "Investigation of low-frequency noise in silicon nanowire MOSFETs," IEEE Electron Device Lett., vol. 30, no. 1, pp. 57-60, Jan. 2009.
14. D. Jimenez, B. Iniguez, J. Sune, L. F. Marsal, J. Pallares, and J. Roig, "Continuous analytical I-V model for surrounding-gate MOSFETs," IEEE Electron Device Lett., vol. 25, no. 8, pp. 571-573, Aug. 2004.
15. J. Brini, G. Ghibaudo, G. Kamarinos, and O. Roux-dit-Buisson, "Scaling down and low-frequency noise in MOSFETs: Are the RTSs the ultimate components of the 1/f noise?" in AIP Conf. Proc., 1993, vol. 282, pp. 31-48.
16. M. Valenza, A. Hoffmann, D. Sodini, and A. Laigle, "Overview of the impact of downscaling technology on 1/f noise in p-MOSFETs to 90 nm," Proc. Inst. Elect. Eng. - Circuits Devices Syst., vol. 151, no. 2, pp. 102-110, Apr. 2004.
17. F. N. Hooge, T. G.M. Kleinpenning, and L. K. J. Vandamme, "Experimental studies on 1/f noise," Rep. Prog. Phys., vol. 44, no. 5, pp. 497-532, 1981.
18. L. K. J. Vandamme and F. N. Hooge, "What do we certainly know about 1/f noise in MOSTs?" IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3070-3085, Nov. 2008.
19. J. Rhayem, D. Rigaud, A. Eyaa, and M. Valenza, "1/f noise in metal-oxide-semiconductor transistors biased in weak inversion," J. Appl. Phys., vol. 89, no. 7, pp. 4192-4194, Apr. 2001.
20. M. V. Haartman and M. Ostling, Low-Frequency Noise in Advanced MOS Devices. Dordrecht, The Netherlands: Springer-Verlag, 2007, pp. 109-110.
21. G. Reimbold, "Modified 1/f trapping noise theory and experiments in MOS transistors biased from weak to strong inversion - Influence of interface states," IEEE Trans. Electron Devices, vol. ED-31, no. 9, pp. 1190-1198, Sep. 1984.