메뉴 건너뛰기




Volumn 53, Issue 7, 2009, Pages 753-759

Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation

Author keywords

FILOX; Frame gate architecture; Short channel effect; Vertical MOSFETs

Indexed keywords

A-FRAMES; ALTERNATIVE METHODS; CHANNEL LENGTH; DRY ETCH DAMAGE; ETCH DAMAGE; FILLET LOCAL OXIDATIONS; FILOX; FRAME-GATE ARCHITECTURE; GATED DIODES; MOSFETS; POLYSILICON GATE ETCH; POLYSILICON GATES; PROTECTIVE OXIDES; SHORT CHANNEL EFFECT; SUBTHRESHOLD; SURROUND GATE; VERTICAL MOSFETS;

EID: 67349259701     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2009.02.016     Document Type: Article
Times cited : (9)

References (27)
  • 1
    • 10644274504 scopus 로고    scopus 로고
    • Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching
    • Masahara M., Liu Y., Hosokawa S., Matsukawa T., Ishii K., Tanoue H., et al. Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching. IEEE Trans Electron Dev 51 (2004) 2078-2085
    • (2004) IEEE Trans Electron Dev , vol.51 , pp. 2078-2085
    • Masahara, M.1    Liu, Y.2    Hosokawa, S.3    Matsukawa, T.4    Ishii, K.5    Tanoue, H.6
  • 2
    • 39749156578 scopus 로고    scopus 로고
    • A low-power, highly scalable, vertical double-gate MOSFET using novel processes
    • Cho H., Kapur P., Kalavade P., and Saraswat K.C. A low-power, highly scalable, vertical double-gate MOSFET using novel processes. IEEE Trans Electron Dev 55 (2008) 632-639
    • (2008) IEEE Trans Electron Dev , vol.55 , pp. 632-639
    • Cho, H.1    Kapur, P.2    Kalavade, P.3    Saraswat, K.C.4
  • 3
    • 0041672285 scopus 로고    scopus 로고
    • An ultrathin vertical channel MOSFET for sub-100 nm applications
    • Liu H., Xiong Z., and Sin J.K.O. An ultrathin vertical channel MOSFET for sub-100 nm applications. IEEE Trans Electron Dev 50 (2003) 1322-1327
    • (2003) IEEE Trans Electron Dev , vol.50 , pp. 1322-1327
    • Liu, H.1    Xiong, Z.2    Sin, J.K.O.3
  • 4
    • 0032305778 scopus 로고    scopus 로고
    • A vertical MOSFET with a leveling, surrounding gate fabricated on a nanoscale island
    • Zheng X, Pak M, Huang J, Choi S, Wang KL. A vertical MOSFET with a leveling, surrounding gate fabricated on a nanoscale island. In: IEEE device research conf dig; 1998. p. 70-1.
    • (1998) IEEE device research conf dig , pp. 70-71
    • Zheng, X.1    Pak, M.2    Huang, J.3    Choi, S.4    Wang, K.L.5
  • 5
    • 67349101042 scopus 로고    scopus 로고
    • Vertical, fully-depleted, surrounding gate MOS-FETs on sub-0.1 um thick pillars
    • Auth CP, Plummer JD. Vertical, fully-depleted, surrounding gate MOS-FETs on sub-0.1 um thick pillars. In: IEEE device research conf dig; 1996. p. 172-5.
    • (1996) IEEE device research conf dig , pp. 172-175
    • Auth, C.P.1    Plummer, J.D.2
  • 12
    • 0032313039 scopus 로고    scopus 로고
    • Optimization of the channel doping profile of vertical sub-100 nm MOSFETs
    • Kaesen F., Fink C., Anil K.G., Hansch W., Doll T., Grabolla T., et al. Optimization of the channel doping profile of vertical sub-100 nm MOSFETs. Thin Solid Films 336 (1998) 309-312
    • (1998) Thin Solid Films , vol.336 , pp. 309-312
    • Kaesen, F.1    Fink, C.2    Anil, K.G.3    Hansch, W.4    Doll, T.5    Grabolla, T.6
  • 15
    • 0036248057 scopus 로고    scopus 로고
    • Sub-100 nm vertical MOSFET with threshold voltage adjustment
    • Mori K., Duong A., and Richardson W.F. Sub-100 nm vertical MOSFET with threshold voltage adjustment. IEEE Trans Electron Dev 49 (2002) 61-66
    • (2002) IEEE Trans Electron Dev , vol.49 , pp. 61-66
    • Mori, K.1    Duong, A.2    Richardson, W.F.3
  • 26
    • 0036566757 scopus 로고    scopus 로고
    • A refined forward gated-diode method for separating front channel hot-carrier-stress induced front and back gate interface and oxide traps in SOI MOSFETs
    • He J., Zhang X., Huang R., and Wang Y. A refined forward gated-diode method for separating front channel hot-carrier-stress induced front and back gate interface and oxide traps in SOI MOSFETs. Semicond Sci Technol 17 (2002) 487-492
    • (2002) Semicond Sci Technol , vol.17 , pp. 487-492
    • He, J.1    Zhang, X.2    Huang, R.3    Wang, Y.4
  • 27
    • 0025388736 scopus 로고
    • Hot-carrier-induced deep-level defects from gated-diode measurements on MOSFETs
    • Speckbacher P., Asenov A., Bollu M., Koch F., and Weber W. Hot-carrier-induced deep-level defects from gated-diode measurements on MOSFETs. IEEE Electron Dev Lett 11 (1990) 95-97
    • (1990) IEEE Electron Dev Lett , vol.11 , pp. 95-97
    • Speckbacher, P.1    Asenov, A.2    Bollu, M.3    Koch, F.4    Weber, W.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.