A low-power, highly scalable, vertical double-gate MOSFET using novel processes

IEEE Transactions on Electron Devices

Volumn 55, Issue 2, 2008, Pages 632-639

  Cho, Hoon ^a   Kapur, Pawan ^a   Kalavade, Pranav ^a,b   Saraswat, Krishna C ^a,c  

^a Stanford University   (United States)

^b INTEL CORPORATION   (United States)

^c BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE   (India)

Author keywords

Drain contact resistance; Nitride spacer process; Self align maskless process; Silicon body thickness (TSi); Vertical double gate MOSFETs (VDFETs)

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CONTACT RESISTANCE; GATES (TRANSISTOR); LITHOGRAPHY; POLARIZATION; SUBSTRATES;

BULK SILICON SUBSTRATE; CHEMICAL-MECHANICAL POLARIZATION; DRAIN CONTACT RESISTANCE; NITRIDE SPACER PROCESS; SELF-ALIGN MASKLESS PROCESS; SHORT-CHANNEL EFFECT;

MOSFET DEVICES;

EID: 39749156578     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.913003     Document Type: Article

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