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Volumn 50, Issue 5, 2006, Pages 897-900

A novel 50 nm vertical MOSFET with a dielectric pocket

Author keywords

Dielectric pocket; Shallow junctions; Short channel effects; Vertical MOSFET

Indexed keywords

DIELECTRIC PROPERTIES; DIFFUSION; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS;

EID: 33744937051     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2006.04.003     Document Type: Article
Times cited : (51)

References (10)
  • 5
    • 0036349380 scopus 로고    scopus 로고
    • Enhanced mobility in 100 nm strained SiGe vertical P-MOSFETs fabricated by UHVCVD
    • Jayanarayanan S., Prins F., Chen X., and Banerjee S. Enhanced mobility in 100 nm strained SiGe vertical P-MOSFETs fabricated by UHVCVD. Mater Res Soc Symp Proc 686 (2002)
    • (2002) Mater Res Soc Symp Proc , vol.686
    • Jayanarayanan, S.1    Prins, F.2    Chen, X.3    Banerjee, S.4
  • 6
    • 0029717332 scopus 로고    scopus 로고
    • Auth CP, Plummer JD. Vertical fully-depleted surrounding gate MOSFETs. IEEE Device Res Conf Paper IV.A; 1996. p. 108-9.
  • 7
    • 84907695515 scopus 로고    scopus 로고
    • Donaghy D, Hall S, Kunz VD, de Groot CH, Ashburn P. Investigating 50 nm channel length MOSFETs containing a dielectric pocket, in a circuit environment. ESSDERC 2002.
  • 9
    • 33744926724 scopus 로고    scopus 로고
    • Taurus-device user guide, version 2003.06, Synopsys Inc.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.