Selectively grown vertical Si MOS transistor with reduced overlap capacitances

Thin Solid Films

Volumn 336, Issue 1-2, 1998, Pages 306-308

  Klaes, D ^a   Moers, J ^a   Tonnesmann A ^a   Wickenhauser S ^a   Vescan, L ^a   Marso, M ^a   Grabolla, T ^b   Grimm, M ^a   Luth H ^a  

^a FORSCHUNGSZENTRUM JÜLICH   (Germany)

^b IHP   (Germany)

Author keywords

Low pressure chemical vapour deposition; Miller capacitance; MOS transistor; Selective epitaxial growth

Indexed keywords

CAPACITANCE; CHEMICAL VAPOR DEPOSITION; EPITAXIAL GROWTH; PHOTOLITHOGRAPHY; REACTIVE ION ETCHING; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SILICA; THIN FILM TRANSISTORS; TRANSCONDUCTANCE;

LOW-PRESSURE CHEMICAL VAPOR DEPOSITION; MILLER CAPACITANCE; SELECTIVE EPITAXIAL GROWTH;

MOSFET DEVICES;

EID: 0032318731     PISSN: 00406090     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0040-6090(98)01248-6     Document Type: Article

References (7)

1. N.N. SIA, Process of the Future, Roadmap of the SIA, Solid-State Technol. (1995) 42.
2. D. Behammer, L. Vescan, R. Loo, J. Moers, A. Muck, H. Lüth, T. Grabolla, Electron. Lett. 32 (1996) 406.
3. L. Risch, Th. Aeugle W. Rösner, Proc. ESSDERC 97, Stuttgart, pp. 34-41.
4. H. Gossner, I. Eisele, L. Risch, Jpn. J. Appl. Phys. 33 (4) (1994) 2423.
5. L. Vescan, in: K. Eberl (Ed.), Low Dimensional Structures Prepared by Epitaxial Growth or Regrowth on Patterned Substrates, Kluwer, Dordrecht, 1995 pp. 173-184.
6. L. Vescan, C. Dieker, A. Hartmann, A. van der Hart, Semicond. Sci. Technol. 9 (1994) 387.
7. R. Loo, L. Vescan, D. Behammer, J. Moers, et al., Thin Solid Films 294 (1997) 267.