Wafer-level packaging with soldered stress-engineered micro-springs

IEEE Transactions on Advanced Packaging

Volumn 32, Issue 2, 2009, Pages 372-378

  Chow, Eugene M ^a   Fork, David K ^a   Chua, Christopher L ^a   Van Schuylenbergh, Koenraad ^a   Hantschel, Thomas ^a  

^a PALO ALTO RESEARCH CENTER   (United States)

Author keywords

Cantilever; Compliant interconnects; Contacts; Fine pitch; flip chip; Memory packaging; Metals; Micro spring; Packaging; Printed circuits; Probing; Resistance; Springs; Stress; Stress engineered; Surface mount technology; Wafer level packaging

Indexed keywords

CANTILEVER; COMPLIANT INTERCONNECTS; CONTACTS; FINE PITCH; FLIP CHIP; MEMORY PACKAGING; MICRO-SPRING; PROBING; RESISTANCE; SPRINGS; WAFER LEVEL PACKAGING;

ATOMIC FORCE MICROSCOPY; AUTOMOBILE PARTS AND EQUIPMENT; BRAZING; DIES; ELECTROMAGNETIC WAVE EMISSION; INTEGRATED CIRCUITS; LEAD; MOUNTINGS; NANOCANTILEVERS; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE; SURFACE MOUNT TECHNOLOGY; THERMAL CYCLING; WELDING;

CHIP SCALE PACKAGES;

EID: 67349130806     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2008.2010507     Document Type: Article

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