Compliant wafer level package for enhanced reliability

Proceedings of International Symposium on High Density Packaging and Microsystem Integration 2007, HDP'07

Volumn , Issue , 2007, Pages

  Guilian, Gao ^a   Haba, Bel ^a   Oganesian, Vage ^a   Honer, Ken ^a   Ovrutsky, David ^b   Rosenstein, Charles ^b   Axelrod, Ekaterina ^b   Hazanovich, Felix ^b   Aksenton, Yulia ^b  

^a Tessera Inc   (United States)

^b Tessera Israel Ltd   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

THERMOMECHANICAL STRESS; WAFER LEVEL PACKAGE (WLP);

COST EFFECTIVENESS; ELECTRONICS PACKAGING; OPTIMIZATION; PRINTED CIRCUIT BOARDS; SOLDERED JOINTS;

WAFER BONDING;

EID: 41049107126     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HDP.2007.4283563     Document Type: Conference Paper

References (8)

1. Patwardhan, V et. al., "Constrained Collapse Solder Joint Formation for Wafer-Level-Chip-Scale Packages to Achieve Reliability Improvement", Proc. of 54th Electronic Components and Technology Conference, 2004, pp1479-1485.
2. http://www.tessera.com/technologies/products/bga_csp/
3. Gardner, G et. al., "Integration of a Low Stress Photopatternable Silicone into a Wafer Level Package", Proc. of 54th Electronic Components and Technology Conference, 2004, pp 170-174.
4. Darling, J, "Wafer Level Burn-in & Test Using Sacrificial Metal as An Interface Medium", Proc. of International Wafer -Level Packaging Conference 04, San Jose, Oct. 2004.
5. Steps, S, "Wafer-Level Burn-in and Test", Proc. of International Wafer -Level Packaging Conference 04, San Jose, Oct. 2004.
6. JEDEC Standard EIA/JESD22-A101-B," Steady-State Temperature Humidity Bias Life Test", Apr. 1997.
7. JEDEC Standard JESD22-A102-C, "Accelerated Moisture Resistance - Unbiased Autoclave", Dec. 2000.
8. IPC Standard 9701A, "Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachment", Feb. 2006.