Good 150 °C retention and fast erase characteristics in charge-trap-engineered memory having a scaled Si3N4 Layer

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Lin, S H ^a   Chin, Albert ^b,c   Yeh, F S ^a   McAlister, S P ^d  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c Nano Electronics Consortium of Taiwan   (Canada)

^d NATIONAL RESEARCH COUNCIL CANADA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE TRAPS; DOUBLE BARRIERS; NON-VOLATILE MEMORIES;

ELECTRON DEVICES; WINDOWS;

FLASH MEMORY;

EID: 64549138356     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796829     Document Type: Conference Paper

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