Improved high temperature retention for charge-trapping memory by using double quantum barriers

IEEE Electron Device Letters

Volumn 29, Issue 4, 2008, Pages 386-388

  Yang, H J ^a   Chin, Albert ^a   Lin, S H ^b   Yeh, F S ^b   McAlister, S P ^c  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^c NATIONAL RESEARCH COUNCIL CANADA   (Canada)

Author keywords

Erase; High ; Nonvolatile memory; Program

Indexed keywords

CHARGE TRAPPING; HIGH TEMPERATURE PROPERTIES; NONVOLATILE STORAGE; SEMICONDUCTOR DEVICE MANUFACTURE;

CHARGE-TRAPPING MEMORY; DOUBLE QUANTUM BARRIERS; MEMORY WINDOW;

SEMICONDUCTOR JUNCTIONS;

EID: 41749084389     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.917811     Document Type: Article

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