Block alignment in 3D floorplan using layered TCG

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn 2006, Issue , 2006, Pages 376-380

  Law, Jill H Y ^a   Young, Evangeline F Y ^a   Ching, Royce L S ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

3D floorplanning; Block alignment

Indexed keywords

CIRCUIT THEORY; ELECTRIC POWER SYSTEM INTERCONNECTION; GATES (TRANSISTOR); INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; PROBLEM SOLVING;

BLOCK ALIGNMENTS; FLOORPLANS; LAYERED TRANSITIVE CLOSURE GRAPH (LTCG); TRANSITIVE CLOSURE GRAPH (TCG);

THREE DIMENSIONAL COMPUTER GRAPHICS;

EID: 33750912778     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1127908.1127994     Document Type: Conference Paper

References (6)

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4. J. Cong, J. Wei, and Y. Zhang. "A Thermal-Driven Floorplanning Algorithm," in Proceedings of the 2004 International Conference on Computer Aided Design, 2004.
5. J. M. Lin and Y. W. Chang, "TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans," in Proceedings of the 38th Conference on Design Automation, 2001.
6. K. Bazargan and R. Kastner and M. Sarrafzadeh, "3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems," in Design Automation for Embedded Systems (DAfES) - RSP'99 Special Issue, 2000.