LP based white space redistribution for thermal via planning and performance optimization in 3D ICs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2008, Pages 209-212

  Li, Xin ^a   Ma, Yuchun ^a   Hong, Xianlong ^a   Dong, Sheqin ^a   Cong, Jason ^b  

^a TSINGHUA UNIVERSITY   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING;

3-D ICS; CIRCUIT DESIGNS; DESIGN AUTOMATION CONFERENCE; DEVICE LAYERS; PERFORMANCE OPTIMIZATIONS; PLANNING METHOD; SOUTH PACIFIC; TARGET REGIONS; TOTAL WIRE LENGTH; WHITE SPACE;

COMPUTATIONAL FLUID DYNAMICS;

EID: 49549102825     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2008.4483942     Document Type: Conference Paper

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