Tuning reconfigurable microarchitectures for power efficiency

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)

Volumn 18, Issue , 2004, Pages 1811-1817

  Dhodapkar, Ashutosh S ^a   Smith, James E ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA CACHES; INSTRUCTION CACHES; PHASE CHANGE; POWER EFFICIENCY;

ALGORITHMS; BENCHMARKING; COMPUTER HARDWARE; OPTIMIZATION; TRANSISTORS; TUNING;

MICROPROCESSOR CHIPS;

EID: 12444347455     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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