A 65nm 95W dual-core multi-threaded Xeon® processor with L3 cache

2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

Volumn , Issue , 2006, Pages 15-18

  Tarn, Simon ^a   Rusu, Stefan ^a   Chang, Jonathan ^a   Vora, Sujal ^a   Cherkauer, Brian ^a   Ayers, David ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); ERROR CORRECTION; OPTIMIZATION;

CACHE SAFE TECHNOLOGY; ERROR CORRECTION CODES (ECC); THERMAL DESIGN;

MICROPROCESSOR CHIPS;

EID: 34250822982     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2006.357840     Document Type: Conference Paper

References (3)

1. S. Rusu et. al., "The Implementation of a Dual-Core Multi-Threaded Xeon® Processor with 16MB L3 Cache", ISSCC Digest of Technical Papers, 2006, pp 102-103.
2. S. Tam et. al., "Clock Generation and Distribution of a Dual-Core Xeon® Processor with 16MB L3 Cache," ISSCC Tech. Digest, 2006, pp 382-383.
3. J. Chang et. al., "The 65nm 16MB On-Die L3 Cache for a Dual Core Multi-Threaded Xeon® Processor", VLSI Circuit Symposium, 2006, pp 158-159.