-
1
-
-
0016973779
-
Optimal code generation for expression trees
-
Jul.
-
A. Aho and S. C. Johnson, "Optimal Code Generation for Expression Trees," Journal of the ACM, vol. 23, pp. 488-501, Jul. 1976.
-
(1976)
Journal of the ACM
, vol.23
, pp. 488-501
-
-
Aho, A.1
Johnson, S.C.2
-
2
-
-
0042635850
-
Automatic application-specific instruction-set extensions under microarchitectural constraints
-
Jun.
-
K. Atasu, L. Pozzi, and P. Ienne, "Automatic Application-Specific Instruction-Set Extensions under Microarchitectural Constraints," in Proceedings of the 40th DAC Design Automation Conference, pp. 256-261, Jun. 2003.
-
(2003)
Proceedings of the 40th DAC Design Automation Conference
, pp. 256-261
-
-
Atasu, K.1
Pozzi, L.2
Ienne, P.3
-
5
-
-
0034174174
-
The garp architecture and C compiler
-
Apr.
-
T. J. Callahan, J. R. Hauser, and J. Wawrzynek, "The Garp Architecture and C Compiler," IEEE Computer, vol. 33(4), pp. 62-69, Apr. 2000.
-
(2000)
IEEE Computer
, vol.33
, Issue.4
, pp. 62-69
-
-
Callahan, T.J.1
Hauser, J.R.2
Wawrzynek, J.3
-
6
-
-
0032681920
-
Cut ranking and pruning: Enabling a general and efficient FPGA mapping solution
-
Feb.
-
J. Cong, C.Wu, and Y. Ding, "Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution," in Proceedings of the 7th ACM/SIGDA International Symposium of FPGAs, pp. 29-35, Feb. 1999.
-
(1999)
Proceedings of the 7th ACM/SIGDA International Symposium of FPGAs
, pp. 29-35
-
-
Cong, J.1
Wu, C.2
Ding, Y.3
-
8
-
-
0033884908
-
Xtensa: A configurable and extensible processor
-
Mar.
-
R. E. Gonzalez, "Xtensa: A Configurable and Extensible Processor," IEEE Micro, vol. 20(2), pp. 60-70, Mar. 2000.
-
(2000)
IEEE Micro
, vol.20
, Issue.2
, pp. 60-70
-
-
Gonzalez, R.E.1
-
9
-
-
0001442299
-
A method for minimizing the number of internal states in incompletely specified machines
-
Jun.
-
A. Grasselli and F. Luccio, "A Method for Minimizing the Number of Internal States in Incompletely Specified Machines," IEEE Transactions on Electronic Computers, vol. 14(3), pp. 350-359, Jun. 1965.
-
(1965)
IEEE Transactions on Electronic Computers
, vol.14
, Issue.3
, pp. 350-359
-
-
Grasselli, A.1
Luccio, F.2
-
10
-
-
0031376640
-
The chimaera reconfigurable functional unit
-
Apr.
-
S. Hauck, T.W. Fry, M.M. Hosler, and J.P. Kao, "The Chimaera Reconfigurable Functional Unit," in Proceedings of Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 87-96, Apr. 1997.
-
(1997)
Proceedings of Annual IEEE Symposium on Field-programmable Custom Computing Machines
, pp. 87-96
-
-
Hauck, S.1
Fry, T.W.2
Hosler, M.M.3
Kao, J.P.4
-
12
-
-
0003898182
-
Reducibility among combinatorial problems
-
EECS Department, University of California, Berkeley, Apr.
-
R. M. Karp, "Reducibility Among Combinatorial Problems," Tech. Rep #3, EECS Department, University of California, Berkeley, Apr. 1972.
-
(1972)
Tech. Rep #3
, vol.3
-
-
Karp, R.M.1
-
13
-
-
0036826798
-
Instruction generation for hybrid reconfigurable systems
-
Oct.
-
R. Kastner, A. Kaplan, S. Ogrenci Memik, and E. Bozorgzaden, "Instruction Generation for Hybrid Reconfigurable Systems," ACM Transactions on Design Automation of Electronic Systems, vol. 7, pp. 605-627, Oct. 2002.
-
(2002)
ACM Transactions on Design Automation of Electronic Systems
, vol.7
, pp. 605-627
-
-
Kastner, R.1
Kaplan, A.2
Memik, S.O.3
Bozorgzaden, E.4
-
15
-
-
0023210698
-
DAGON: Technology binding and local optimization by DAG matching
-
Jun.
-
K. Keutzer, "DAGON: Technology Binding and Local Optimization by DAG Matching," in Proceedings of the 24th Design Automation Conference, pp. 341-347, Jun. 1987.
-
(1987)
Proceedings of the 24th Design Automation Conference
, pp. 341-347
-
-
Keutzer, K.1
-
16
-
-
0029488328
-
Instruction selection using binate covering for code size optimization
-
Nov.
-
S. Liao, S. Devadas, K. Keutzer, and S. Tjiang, "Instruction Selection Using Binate Covering for Code Size Optimization," in Proceedings of International Conference on Computer Aided Design, pp. 393-399, Nov. 1995.
-
(1995)
Proceedings of International Conference on Computer Aided Design
, pp. 393-399
-
-
Liao, S.1
Devadas, S.2
Keutzer, K.3
Tjiang, S.4
-
17
-
-
0002603293
-
Practical graph isomorphism
-
B. D. McKay, "Practical Graph Isomorphism," Congressus Numerantium, vol 30, pp. 45-87, 1981.
-
(1981)
Congressus Numerantium
, vol.30
, pp. 45-87
-
-
McKay, B.D.1
-
19
-
-
84942512878
-
Automatic instruction-set extension and utilization for embedded processors
-
Jun.
-
A. Peymandoust, L. Pozzi, P. Ienne, and G. De Micheli, "Automatic Instruction-Set Extension and Utilization for Embedded Processors," in Proceedings of the 14th International Conference on Application-specific Systems, Architectures and Processors, Jun. 2003.
-
(2003)
Proceedings of the 14th International Conference on Application-specific Systems, Architectures and Processors
-
-
Peymandoust, A.1
Pozzi, L.2
Ienne, P.3
De Micheli, G.4
-
20
-
-
0003623384
-
Logic synthesis for VLSI design
-
Ph.D. Thesis, U. C. Berkeley
-
R. L. Rudell, "Logic Synthesis for VLSI Design," Ph.D. Thesis, U. C. Berkeley, ERL Memo 89/49, 1989.
-
(1989)
ERL Memo
, vol.89
, Issue.49
-
-
Rudell, R.L.1
-
21
-
-
0016974389
-
A fast backtracking algorithm to test directed graphs for isomorphism using distance matrices
-
Jul.
-
D. C. Schmidt and L. E. Druffel, "A Fast Backtracking Algorithm to Test Directed Graphs for Isomorphism Using Distance Matrices," Journal of the ACM, vol. 23 no. 3, pp. 433-445, Jul. 1976.
-
(1976)
Journal of the ACM
, vol.23
, Issue.3
, pp. 433-445
-
-
Schmidt, D.C.1
Druffel, L.E.2
-
22
-
-
0038336002
-
Optimum and heuristic transformation techniques for simultaneous optimization of latency and throughput
-
Mar.
-
M. B. Srivastava and M. Potkonjak, "Optimum and Heuristic Transformation Techniques for Simultaneous Optimization of Latency and Throughput," IEEE Transactions on VLSI Systems, vol. 3, no. 1, pp. 2-19, Mar. 1995.
-
(1995)
IEEE Transactions on VLSI Systems
, vol.3
, Issue.1
, pp. 2-19
-
-
Srivastava, M.B.1
Potkonjak, M.2
-
23
-
-
0003268059
-
DSPStone - A DSP-oriented benchmarking methodology
-
Oct.
-
V. Zivojinovic, J. M. Velarde, C. Schlager, and H. Meyr, "DSPStone - A DSP-oriented Benchmarking Methodology," in Proceedings of International Conference on Signal Processing Application Technology, pp. 715-720, Oct. 1994.
-
(1994)
Proceedings of International Conference on Signal Processing Application Technology
, pp. 715-720
-
-
Zivojinovic, V.1
Velarde, J.M.2
Schlager, C.3
Meyr, H.4
-
24
-
-
2442577598
-
-
Altera Corp., http://www.altera.com.
-
-
-
-
25
-
-
84862488213
-
-
Nauty Package, http://cs.anu.edu.au/people/bdm/nauty.
-
Nauty Package
-
-
-
26
-
-
0346237861
-
-
SUIF Compiler, http://suif.stanford.edu.
-
SUIF Compiler
-
-
-
27
-
-
2442459497
-
-
Tensilica Inc., http://www.tensilica.com.
-
-
-
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