Forecasting-based dynamic virtual channels allocation for power optimization of network-on-chips

Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems

Volumn , Issue , 2009, Pages 151-156

  Rahmani, Amir Mohammad ^a   Daneshtalab, Masoud ^a   Afzai Kusha, Ali ^a   Safari, Saeed ^a   Pedram, Masoud ^b  

^a UNIVERSITY OF TEHRAN   (Iran)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER UTILIZATIONS; DATA COMMUNICATION RATES; DYNAMIC POWER MANAGEMENTS; IN NETWORKS; INPUT CHANNELS; NETWORK ON CHIPS; POWER CONSUMPTION; POWER OPTIMIZATIONS; POWER OVERHEADS; SIMULATION RESULTS; TRAFFIC CONDITIONS; TRAFFIC LOADS; TRAFFIC PROFILES; VIRTUAL CHANNELS;

COMMUNICATION CHANNELS (INFORMATION THEORY); DISTRIBUTED COMPUTER SYSTEMS; ELECTRIC LOAD FORECASTING; ELECTRIC POWER MEASUREMENT; ELECTRIC POWER UTILIZATION; ENERGY MANAGEMENT; FAULT TOLERANT COMPUTER SYSTEMS; INDUSTRIAL MANAGEMENT; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; ROUTERS;

EMBEDDED SYSTEMS;

EID: 62949219981     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2009.87     Document Type: Conference Paper

References (20)

1. L. Benini and G. D. Micheli, "Networks on chips: A new SoC paradigm," IEEE Computer, vol. 35, pp. 70-78, January, 2002.
2. W.J. Dally et al., "Route Packets, Not Wires: On-Chip Interconnection Networks," in Proc. of the DAC Conference, pp.684-689, 2001.
3. S. Heo and K. Asanovic, "Replacing global wires with an onchip network: a power analysis," in Proc. of the ISLPED Conference, pp. 369-374, 2005.
4. R. Kumar, V. Zyuban, and D. M. Tullsen, "Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling," in Proc. of ISCA Conference, pp. 408-419, 2005.
5. W. Hangsheng, L. S. Peh, and S. Malik, "Power-driven design of router microarchitectures in on-chip networks," in Proc. of the MICRO Conference, pp. 105-116, 2003.
6. T. T. Ye, L. Benini, and G. De Micheli, "Analysis of power consumption on switch fabrics in network routers," in Proc. of DAC, pp. 524-529, 2002.
7. L. M. Ni and P. K. McKinley. A survey of wormhole routing techniques in direct networks. IEEE Computer, 26:62{76, Feb. 1993.
8. W. J. Dally, "Virtual-channel flow control," in Proc. of the ISCA, pp. 60-68, 1990.
9. W. J. Dally and C. L. Seitz, "Deadlock-free message routing in multiprocessor interconnection networks," IEEE Transactions on Computers, pp. 547-553, 1987.
10. C.A. Zeferino, M.E. Kreutz, A.A. Susin, "RASoC: A Router Soft-Core for Networks-on-Chip," DATE, Feb. 2004, pp. 198- 203.
11. W. J. Dally and C. L. Seitz, "The torus routing chip," Journal of Distributed Computing, vol. 1(3), pp. 187-196, 1986.
12. M. Li, Q.-A. Zeng, and W.-B. Jone, "DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip," in Proc. of the DAC Conference, July 2006, pp. 849-852.
13. G. M. Chiu, "The odd-even turn model for adaptive routing," IEEE Trans. on Parallel and Distributed Systems, 11:729 - 738, July 2000.
14. E.S .Shin, V.J. Mooney, G.F. Riley, "Round-robin Arbiter Design and Generation," in Proc. of International Symposium on System Synthesis, 2002, pp. 243-248.
15. A. Bystrov, D. J. Kinniment, and A. Yakovlev, "Priority Arbiters," in Proc. of the ASYNC Conference, 2000, pp. 128-137.
16. W. J. Dally and C. L. Seitz, "Deadlock-free message routing in multiprocessor interconnection networks," IEEE Transactions on Computers, vol. C-36(5), pp. 547-553, 1987.
17. S. Banerjee, and N. Dutt, "FIFO Power Optimization for OnChip Networks," in Proc. of the 14th GLSVLSI Conference, 2004, pp. 187-191.
18. th HPCA Conference, Feb. 2003, pp. 91-102.
19. R .J. Tersine, Principles of Inventory & Material Management, Fourth Edition, Prentice Hall PTR, August 1994.
20. M. Rezazad, H. Sarbazi-azad, "The Effect of Virtual Channel Organization on the Performance of Interconnection Networks," in Proc. of the 19th IPDPS Conference, April 2005, pp. 264-271.