FIFO power optimization for on-chip networks

Proceedings of the ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2004, Pages 187-191

  Banerjee, Sudarshan ^a   Dutt, Nikil ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

FIFO; Low power design; On chip networks; Shared memory; Switches; Wide flits

Indexed keywords

COMPUTER ARCHITECTURE; DATA TRANSFER; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; OPTIMIZATION; PACKET NETWORKS; PARALLEL PROCESSING SYSTEMS; ROUTERS;

FIFO; LOW POWER DESIGN; ON-CHIP NETWORKS; SHARED MEMORY SWITCHES; SYSTEM ON CHIP (SOC); WIDE FLITS;

COMPUTER NETWORKS;

EID: 2942650264     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/988952.988998     Document Type: Conference Paper

References (20)

1. HS Wang, X Zhu, LS Peh, S Malik, "Orion: A Power-performance Simulator for Interconnection Networks" IEEE Micro, 2002.
2. HS Wang, LS Peh, S Malik, "Power-driven design of router Microarchitectures in On-chip networks" IEEE Micro, 2003.
3. P Guerrier, A Greinier, "A generic architecture for On-Chip Packet-Switched Interconnections" DATE, 2000
4. WJ Dally, B Towles, "Route packets, not wires: on-chip interconnection networks" DAC, 2001
5. DE Culler, JP Singh, "Parallel Computer Architecture; A Hardware/Software Approach" Morgan Kaufmann Publishers, 1998
6. SJE Wilton, N Jouppi, "CACTI: An enhanced Cache Access and Cycle Time Model" IEEE. Jrnl. Solid-State Circuits, Vol. 31 No 5, May 1996
7. D Brooks, V Tiwari, M Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations" ISCA, 2000
8. JP Singh, WD Weber, A Gupta, "SPLASH: Stanford Parallel Applications for Shared-Memory" ACM SIGARCH Computer Architecture News, Vol 20, No 1, 1992
9. CJ Hughes, VS Pai, P Ranganathan, S Adve, "RSIM: simulating shared-memory multiprocessors with ILP processors" Computer Vol 35, Issue 2, Feb 2002
10. TT Ye, L Benini, GD Micheli, "Packetized On-chip Interconnect Communication analysis for MPSoC" DATE, 2003
11. A Kumar, LN Bhuyan, "Evaluating virtual channels for Cache-Coherent shared memory Multiprocessors" International Conference on Supercomputing, 1996
12. S S Mukherjee, P Bannon, S Lang, A Spink, D Webb, "The Alpa 21364 network architecture" IEEE Micro Vol 22, No 1, 2002
13. M Pedram, "Power Minimization in IC Design: Principles and Applications" ACM TODAES Vol 1, No 1, Jan 1996
14. AP Chandrakasan, RW Brodersen, "Minimizing power consumption in digital circuits" Proc. of the IEEE Vol 83, No 4, Apr 1995
15. L Benini, GD Micheli, "Networks on Chips: A new paradigm for System on Chip Design" DATE, 2002
16. C Patel, S Chai, S Yalamanchili, D Shimmel, "Power constrained design of multiprocessor interconnection networks" IEEE International Conference on Computer Design, 1997
17. AG Wassal, MA Hassan, "Low-power system-level design of VLSI packet switching fabrics" IEEE Trans on CAD of Integrated Circuits and Systems", June 2001
18. J Duato, S Yalamanchili, L Ni, "Interconnection networks: an engineering approach" IEEE Computer Society Press, 1997
19. Li-Shiuan Peh, "Flow Control and Micro-Architectural Mechanisms for Extending the Performance of Interconnection Networks" Ph.D. Thesis, Stanford University August 2001.
20. MJ Karol, MG Hluchy, SP Morgan, "Input versus Output Queuing on a Space-Division Packet Switch" IEEE Trans on Communications, Dec 1987