Designing Fault-Secure Parallel Encoders for Systematic Linear Error Correcting Codes

IEEE Transactions on Reliability

Volumn 52, Issue 4, 2003, Pages 492-500

  Piestrak, Stanislław J ^a   Dandache, Abbas ^b   Monteiro, Fabrice ^b  

^a WROCLAW UNIVERSITY OF TECHNOLOGY   (Poland)

^b UNIVERSITÉ DE LORRAINE   (France)

Author keywords

Fault secure circuit; Fault tolerance; Parallel encoder; Self checking circuit; Systematic linear error correcting code

Indexed keywords

COMPUTER SYSTEMS; DATA COMMUNICATION SYSTEMS; DECODING; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; ITERATIVE METHODS; MICROELECTRONICS; POLYNOMIALS; VLSI CIRCUITS;

FAULT-SECURE CIRCUITS; PARALLEL ENCODERS; SELF-CHECKING CIRCUITS;

ERROR CORRECTION;

EID: 0742290123     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/TR.2003.821940     Document Type: Article

References (24)

1. W. C. Carter and P. R. Schneider, "Design of dynamically checked computers," in Proc. IFIP Conf., Edinburgh, Scotland, August 1968, pp. 878-883.
2. D. A. Anderson and G. Metze, "Design of totally self-checking check circuits for m-out-of-n codes," IEEE Trans. Comput., vol. C-22, pp. 263-269, March 1973.
3. M. Y. Hsiao, A. M. Patel, and D. K. Pradhan, "Store address generator with on-line fault-detection capability," IEEE Trans. Comput., vol. C-26, pp. 1144-1147, Nov. 1977.
4. D. K. Pradhan, M. Y. Hsiao, A. M. Patel, and S. Y. Su, "Shift register designed for on-line fault-detection," in Dig. Pap. 8th Int. FTC Symp., Toulouse, France, June 1978, pp. 173-178.
5. D. J. Lu, "Self-checking linear shift registers," in Dig. Pap. 10th Int. FTC Symp., Kyoto, Japan, Oct. 1980, pp. 269-271.
6. L.-T. Wang, "Autonomous linear feedback shift register with on-line fault-detection capability," in Dig. Pap. 12th Int. FTC Symp., Santa Monica, CA, June 1982, pp. 311-314.
7. A. M. Patel, "A multi-channel CRC register," in Proc. AFIPS SJCC'71, 1971, pp. 11-14.
8. A. Perez, "Parallel CRC generation," IEEE Micro, vol. 3, pp. 40-50, June 1983.
9. T. V. Ramabadran and S. S. Gaitonde, "A tutorial on CRC computations," IEEE Micro, vol. 8, pp. 62-75, August 1988.
10. G. Albertengo and R. Sisto, "Parallel CRC generation," IEEE Micro, vol. 10, pp. 63-71, October 1990.
11. T.-B. Pei and C. Zukowski, "High speed parallel CRC circuits in VLSI," IEEE Trans. Communications, vol. 40, pp. 653-657, April 1992.
12. R. J. Glaise and J. Jacquart, "Fast CRC calculation," in Proc. ICCD'93, Cambridge, MA, October 3-6, 1993, pp. 602-605.
13. M. Braun, J. Friedrich, F. Grün, and J. Lembert, "Parallel CRC computation in FPGAs," in Proc. FPL'96 - 6th Int. Workshop on Field-Programmable Logic: Smart Applications, New Paradigms and Compilers, Darmstadt, Germany, September 23-25, 1996, pp. 156-165.
14. S. L. Ng and B. Dewar, "Parallel realization of the ATM cell header CRC," Computer Communications, vol. 19, pp. 257-263, March 1996.
15. R. J. Glaise, "A two-step computation of cyclic redundancy code CRC-32 for ATM networks," IBM J. Res. Develop., vol. 41, pp. 705-709, 1997.
16. R. F. Hobson and K. Cheung, "A high-performance CMOS 32-bit parallel CRC engine," IEEE J. Solid State Circuits, vol. 34, pp. 233-235, Feb. 1999.
17. F. Monteiro, A. Dandache, and B. Lepley, "Fast configurable polynomial division for error control coding applications," in Proc. IOLTW 2001, Taormina, Italy, July 9-11, 2001, pp. 158-161.
18. T. K. Matsushima, T. Matsushima, and S. Hirasawa, "Parallel encoder and decoder architectures for cyclic codes," IEICE Trans. A, vol. E79-A, pp. 1313-1323, September 1996.
19. K. Kobayashi, K. Yamano, H. Kokubun, and K. Kobayashi, "A 50 MHz CMOS pipelined majority logic decoder for (1 057 813) difference-set cyclic code," IEICE Trans. A, vol. E79-A, pp. 1060-1067, July 1996.
20. T. Vallino, S. J. Piestrak, A. Dandache, F. Monteiro, and B. Lepley, "The study of a new parallel architecture dedicated to the family of the difference set cyclic codes," in Proc. 5th IEEE Int. On-Line Testing Workshop, Rhodes, Greece, July 5-7, 1999, pp. 237-239.
21. R. E. Blahut, Theory and Implementation of Error Correcting Codes. Reading, MA: Addison-Wesley, 1983.
22. D. Lamer, "Sun flips bits in chips," Electronics Times, no. 878, pp. 72-24, November 1997.
23. J. F. Ziegler, "Terrestrial cosmic rays intensities," IBM J. Res. Develop., vol. 42, pp. 117-139, 1998.
24. M. Nicolaidis, "Time redundancy based soft-error tolerance to rescue nanometer technologies," in Proc. 17th VTS, Dana Point, California, April 25-29, pp. 86-94.