Fault Tolerant Nano-Memory with Fault Secure Encoder and Decoder

Nano-Net 2007 - Proceedings of the 2nd International Conference on Nano-Networks

Volumn , Issue , 2007, Pages

  Naeimi, Helia ^a   DeHon, Andre ^b  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CODES (SYMBOLS); DIGITAL STORAGE; ERROR CORRECTION; FAILURE RATE; FAULT TOLERANCE; NANOWIRES; NETWORK ARCHITECTURE; SIGNAL ENCODING;

DETECTOR DESIGN; ENCODERS AND DECODERS; ERROR CORRECTING CODE; EUCLIDEAN GEOMETRY; FAULT SECURE; FAULT-TOLERANT; GEOMETRY ERRORS; NANO MEMORY; STORAGE ELEMENTS; TRANSIENT FAULTS;

MEMORY ARCHITECTURE;

EID: 62949232960     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.4108/ICST.NANONET2007.2029     Document Type: Conference Paper

References (20)

1. Y. Chen, G.-Y. Jung, D. A. A. Ohlberg, X. Li, D. R. Stewart, J. O. Jeppesen, K. A. Nielsen, J. F. Stoddart, and R. S. Williams. Nanoscale Molecular-Switch Crossbar Circuits. Nanotechnology, 14:462–468, 2003.
2. Y. Cui, X. Duan, J. Hu, and C. M. Lieber. Doping and Electrical Transport in Silicon Nanowires. Journal of Physical Chemistry B, 104(22):5213–5216, June 8 2000.
3. Y. Cui, L. J. Lauhon, M. S. Gudiksen, J. Wang, and C. M. Lieber. Diameter-Controlled Synthesis of Single Crystal Silicon Nanowires. Applied Physics Letters, 78(15):2214–2216, 2001.
4. A. DeHon. Law of Large Numbers System Design. In S. K. Shukla and R. I. Bahar, editors, Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, chapter 7, pages 213–241. Kluwer Academic Publishers, Boston, 2004.
5. A. DeHon. Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches. IEEE Transactions on Nanotechnology, 4(6):681–687, 2005.
6. A. DeHon. Design of Programmable Interconnect for Sublithographic Programmable Logic Arrays. In Proceedings of the International Symposium on Field-Programmable Gate Arrays, pages 127–137, February 2005.
7. A. DeHon. Nanowire-Based Programmable Architectures. ACM Journal on Emerging Technologies in Computing Systems, 1(2):109–162, 2005.
8. A. DeHon, S. C. Goldstein, P. J. Kuekes, and P. Lincoln. Non-Photolithographic Nanoscale Memory Density Prospects. IEEE Transactions on Nanotechnology, 4(2):215–228, 2005.
9. A. DeHon, P. Lincoln, and J. Savage. Stochastic Assembly of Sublithographic Nanoscale Interfaces. IEEE Transactions on Nanotechnology, 2(3):165–174, 2003.
10. A. DeHon and M. J. Wilson. Nanowire-Based Sublithographic Programmable Logic Arrays. In Proceedings of the International Symposium on Field-Programmable Gate Arrays, pages 123–132, February 2004.
11. M. Forshaw, R. Stadler, D. Crawley, and K. Nikolić. A Short Review of Nanoelectronic Architectures. Nanotechnology, 15:S220–S223, 2004.
12. R. G. Gallager. Low-Density Parity-Check Codes. MIT Press, 1963.
13. 11 Bits per Square Centimetre. Nature, 445:414–417, January 25 2006.
14. J. Kim and L. Kish. Error Rate In Current-Controlled Logic Processors With Shot Noise. Fluctuation and Noise Letters, 4(1):83–86, 2004.
15. D. E. Knuth. The Art of Computer Programming. Addison Wesley, second edition, 2000.
16. S. Lin and D. J. Costello. Error Control Coding. Prentice Hall, second edition, 2004.
17. R. J. McEliece. The Theory of Information and Coding. Cambridge University Press, 2002.
18. H. Naeimi and A. DeHon. Fault Secure Encoder and Decoder for Memory Applications. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, September 2007.
19. A. Saleh, J. Serrano, and J. Patel. Reliability of Scrubbing Recovery-Techniques for Memory Systems. IEEE Transaction on Reliability, 39(1):114–122, 1996.
20. S. Williams and P. Kuekes. Demultiplexer for a Molecular Wire Crossbar Network. United States Patent Number: 6,256,767, July 3 2001.