Run-time data-dependent defect tolerance for hybrid CMOS/nanodevice digital memories

IEEE Transactions on Nanotechnology

Volumn 7, Issue 2, 2008, Pages 217-222

  Sun, Fei ^a,b,c   Feng, Lu ^b   Zhang, Tong ^a,b  

^a IEEE

^b RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^c MARVELL SEMICONDUCTOR INC   (United States)

Author keywords

CMOS; Defect tolerance; Digital memory; Error control codes; Nano device; Storage capacity

Indexed keywords

COMPUTER SIMULATION; DATA STRUCTURES; DIGITAL STORAGE; REDUNDANCY;

DEFECT TOLERANCE; ERROR CONTROL CODES; NANO DEVICES; STORAGE CAPACITY;

CMOS INTEGRATED CIRCUITS;

EID: 41149117071     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2007.914972     Document Type: Conference Paper

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