Study of the effects of multibit error correction codes on the reliability of memories in the presence of MBUs

IEEE Transactions on Device and Materials Reliability

Volumn 9, Issue 1, 2009, Pages 31-39

  Reviriego, Pedro ^a   Maestro, Juan Antonio ^a  

^a UNIVERSIDAD ANTONIO DE NEBRIJA   (Spain)

Author keywords

Memory; Multibit error correction codes; Multiple bit upsets (MBUs); Reliability

Indexed keywords

CODES (SYMBOLS); DATA STORAGE EQUIPMENT; ELECTRIC NETWORK ANALYSIS; ERROR DETECTION; QUALITY ASSURANCE; RELIABILITY ANALYSIS; URANIUM POWDER METALLURGY;

ARRIVAL RATES; DEVELOPED MODELS; ERROR DETECTION CODES; MEMORY; MULTI BITS; MULTIBIT ERROR CORRECTION CODES; MULTIPLE BIT UPSETS (MBUS); POSSIBLE SOLUTIONS; SIMULATION RESULTS; SINGLE EVENT UPSETS; SINGLE EVENTS; SOFT ERRORS;

ERROR CORRECTION;

EID: 61849088853     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2008.2007647     Document Type: Article

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