Parallel image processing field programmable gate array for real time image processing system

Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003

Volumn , Issue , 2003, Pages 372-374

  Sugimura, Takeaki ^a   Shim, Jeoungchill ^a   Kurino, Hiroyuki ^a   Koyanagi, Mitsumasa ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC GATES; RECONFIGURABLE HARDWARE;

CMOS TECHNOLOGY; CONFIGURATION MEMORY; LOGIC BLOCKS; PARALLEL IMAGE PROCESSING; REAL-TIME IMAGE PROCESSING; RECONFIGURABLE INTERCONNECTION NETWORKS; TEST CHIPS;

IMAGE PROCESSING;

EID: 84888277405     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2003.1275779     Document Type: Conference Paper

References (2)

1. D. Kawae, H. Kurino, and M. Koyanagi, "Design of Real Time Micro-Vision System LSI with Three-Dimensional Structure", Proc. Of the Workshop on System Integration of Mixed Technologies, pp. 229-234, 1998.
2. Andre DeHon, "Reconfigurable Architectures for General-Purpose Computing", MIT A. I. Technical Report No, 1586, October, 1996.