Power-performance trade-offs for reconfigurable computing

Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, CODES+ISSS 2004

Volumn , Issue , 2004, Pages 116-121

  Noguera, Juanjo ^a   Badia, Rosa M ^b  

^a HEWLETT PACKARD COMPANY   (United States)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Dynamically reconfigurable architectures; HW SW partitioning; Power performance trade offs; Task configuration scheduling

Indexed keywords

ALGORITHMS; CAMERAS; DATA PROCESSING; ENERGY EFFICIENCY; IMAGE PROCESSING; PROGRAMMABLE LOGIC CONTROLLERS; SCHEDULING;

CONFIGURATION SCHEDULING; DYNAMICALLY RECONFIGURABLE ARCHITECTURES; HARDWARE PARTITIONING; POWER-PERFORMANCE TRADE-OFFS; SOFTWARE PARTITIONING; TASK SCHEDULING;

EMBEDDED SYSTEMS;

EID: 16244407759     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016720.1016751     Document Type: Conference Paper

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