Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 9, 2006, Pages 1010-1023

  Vikram, Krishna N ^a,b   Vasudevan, Vinita ^a,c  

^a IEEE   (India)

^b Siemens Ltd India   (India)

^c INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

Author keywords

Data parallel tasks; Divisible load theory; Dynamically reconfigurable logic (DRL); Hybrid processor architectures; Partial reconfiguration

Indexed keywords

DATA PARALLEL TASKS; DIVISIBLE LOAD THEORY; DYNAMICALLY RECONFIGURABLE LOGIC (DRL); HYBRID PROCESSOR ARCHITECTURES; PARTIAL RECONFIGURATION;

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; DATA RECORDING; FIELD PROGRAMMABLE GATE ARRAYS; MAPPING;

PROGRAM PROCESSORS;

EID: 33750575399     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.884052     Document Type: Article

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