-
1
-
-
0034174010
-
Video image processing with the Sonic architecture
-
Haynes, S.D., Stone, J., Cheung, P.Y.K., Luk, W.: Video image processing with the Sonic architecture. IEEE Computer 33 (2000) 50-57
-
(2000)
IEEE Computer
, vol.33
, pp. 50-57
-
-
Haynes, S.D.1
Stone, J.2
Cheung, P.Y.K.3
Luk, W.4
-
2
-
-
0001286148
-
Data-reuse and parallel embedded architectures for low-power, real-time multimedia applications
-
Soudris, D., Zervas, N.D., Argyriou, A., Dasygenis, M., Tatas, K., Goutis, C., Thanailakis, A.: Data-reuse and parallel embedded architectures for low-power, real-time multimedia applications. In: International Workshop - Power and Timing Modeling, Optimization and Simulation. (2000)
-
(2000)
International Workshop - Power and Timing Modeling, Optimization and Simulation
-
-
Soudris, D.1
Zervas, N.D.2
Argyriou, A.3
Dasygenis, M.4
Tatas, K.5
Goutis, C.6
Thanailakis, A.7
-
3
-
-
0027847339
-
The Splash 2 processor and applications
-
Arnold, J.M., Buell, D.A., Hoang, D.T., Pryor, D.V., Shirazi, N., Thistle, M.R.: The Splash 2 processor and applications. In: IEEE International Conference on Computer Design: VLSI in Computers and Processors. (1993)
-
(1993)
IEEE International Conference on Computer Design: VLSI in Computers and Processors
-
-
Arnold, J.M.1
Buell, D.A.2
Hoang, D.T.3
Pryor, D.V.4
Shirazi, N.5
Thistle, M.R.6
-
4
-
-
0030104367
-
Programmable active memories: Reconfigurable systems come of age
-
Vuillemin, J.E., Bertin, P., Roncin, D., Shand, M., Touati, H.H., Boucard, P.: Programmable active memories: Reconfigurable systems come of age. IEEE Transactions on VLSI Systems 4 (1996) 56-69
-
(1996)
IEEE Transactions on VLSI Systems
, vol.4
, pp. 56-69
-
-
Vuillemin, J.E.1
Bertin, P.2
Roncin, D.3
Shand, M.4
Touati, H.H.5
Boucard, P.6
-
5
-
-
0029255778
-
Real-time image processing on a custom computing platform
-
Athanas, P.M., Abbott, A.L.: Real-time image processing on a custom computing platform. IEEE Computer 28 (1995) 16-24
-
(1995)
IEEE Computer
, vol.28
, pp. 16-24
-
-
Athanas, P.M.1
Abbott, A.L.2
-
6
-
-
0034174174
-
The Garp architecture and C compiler
-
Callahan, T.J., Hauser, J.R., Wawrzynek, J.: The Garp architecture and C compiler. IEEE Computer 33 (2000) 62-69
-
(2000)
IEEE Computer
, vol.33
, pp. 62-69
-
-
Callahan, T.J.1
Hauser, J.R.2
Wawrzynek, J.3
-
8
-
-
0034174187
-
PipeRench: A reconfigurable architecture and compiler
-
Goldstein, S.C., Schmit, H., Budiu, M., Cadambi, S., Moe, M., Taylor, R.R.: PipeRench: A reconfigurable architecture and compiler. IEEE Computer 33 (2000) 70-77
-
(2000)
IEEE Computer
, vol.33
, pp. 70-77
-
-
Goldstein, S.C.1
Schmit, H.2
Budiu, M.3
Cadambi, S.4
Moe, M.5
Taylor, R.R.6
-
9
-
-
0031236158
-
Baring it all to software: RAW machines
-
Waingold, E., Taylor, M., Srikrishna, D., Sarkar, V., Lee, W., Lee, V., Kim, J., Frank, M., Finch, P., Barua, R., Babb, J., Amarasinghe, S., Agarwal, A.: Baring it all to software: RAW machines. IEEE Computer 30 (1997) 86-93
-
(1997)
IEEE Computer
, vol.30
, pp. 86-93
-
-
Waingold, E.1
Taylor, M.2
Srikrishna, D.3
Sarkar, V.4
Lee, W.5
Lee, V.6
Kim, J.7
Frank, M.8
Finch, P.9
Barua, R.10
Babb, J.11
Amarasinghe, S.12
Agarwal, A.13
-
11
-
-
0036054393
-
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
-
Horta, E.L., Lockwood, J.W., Taylor, D.E., Parlour, D.: Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. In: Design Automation Conference. (2002)
-
(2002)
Design Automation Conference
-
-
Horta, E.L.1
Lockwood, J.W.2
Taylor, D.E.3
Parlour, D.4
-
13
-
-
0037979478
-
Dynamically reconfigurable system-on-programmable-chip
-
Kalte, H., Langen, D., Vonnahme, E., Brinkmann, A., Rückert, U.: Dynamically reconfigurable system-on-programmable-chip. In: Euromicro Workshop on Parallel, Distributed and Network-based Processing. (2002)
-
(2002)
Euromicro Workshop on Parallel, Distributed and Network-based Processing
-
-
Kalte, H.1
Langen, D.2
Vonnahme, E.3
Brinkmann, A.4
Rückert, U.5
-
14
-
-
0036149420
-
Networks on chips: A new SoC paradigm
-
Benini, L., De Micheli, G.: Networks on chips: A new SoC paradigm. IEEE Computer 35 (2002) 70-78
-
(2002)
IEEE Computer
, vol.35
, pp. 70-78
-
-
Benini, L.1
De Micheli, G.2
-
15
-
-
0034848112
-
Route packets, not wires: On-chip interconnection networks
-
Dally, W.J., Towles, B.: Route packets, not wires: On-chip interconnection networks. In: Design Automation Conference. (2001)
-
(2001)
Design Automation Conference
-
-
Dally, W.J.1
Towles, B.2
-
16
-
-
0038598363
-
UltraSONIC: A reconfigurable architecture for video image processing
-
Haynes, S.D., Epsom, H.G., Cooper, R.J., McAlpine, P.L.: UltraSONIC: a reconfigurable architecture for video image processing. In: Field-Programmable Logic and Applications. (2002)
-
(2002)
Field-Programmable Logic and Applications
-
-
Haynes, S.D.1
Epsom, H.G.2
Cooper, R.J.3
McAlpine, P.L.4
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