Runtime assignment of reconfigurable hardware components for image processing pipelines

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2003-January, Issue , 2003, Pages 173-182

  Quinn, H ^a   King, L A S ^b   Leeser, M ^a   Meleis, W ^a  

^a Northeastern University   (United States)

^b Brown University College of the Holy Cross   (United States)

Author keywords

Acceleration; Algorithm design and analysis; Application software; Field programmable gate arrays; Hardware; Image analysis; Image processing; Pipelines; Runtime; Software algorithms

Indexed keywords

ACCELERATION; ALGORITHMS; APPLICATION PROGRAMS; COMBINATORIAL OPTIMIZATION; COMPUTER HARDWARE; COMPUTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; HARDWARE-SOFTWARE CODESIGN; HEURISTIC METHODS; IMAGE ANALYSIS; IMAGE PROCESSING; LOGIC GATES; OPTIMIZATION; PIPELINES; RECONFIGURABLE HARDWARE;

ALGORITHM DESIGN AND ANALYSIS; HARDWARE ACCELERATION; IMAGE PROCESSING ALGORITHM; IMAGE PROCESSING APPLICATIONS; IMAGE PROCESSING PIPELINE; RUNTIMES; SOFTWARE ALGORITHMS; SOFTWARE IMPLEMENTATION;

PIPELINE PROCESSING SYSTEMS;

EID: 84942926728     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2003.1227253     Document Type: Conference Paper

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