An utilization driven framework for energy efficient caches

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 5374 LNCS, Issue , 2008, Pages 583-594

  Ramaswamy, Subramanian ^a   Yalamanchili, Sudhakar ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; MICROPROCESSOR CHIPS;

CACHE MANAGEMENT; COUPLING VOLTAGE; DIE SIZE; DRIVE VOLTAGES; ENERGY DELAY PRODUCT (EDP); ENERGY EFFICIENT; LINE UTILIZATION; PHASE CACHE; PRIMARY DESIGN;

ENERGY EFFICIENCY;

EID: 58449101622     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-89894-8_50     Document Type: Conference Paper

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