High-performance poly-silicon TFTs using a high-κ PrTiO3 gate dielectric

IEEE Electron Device Letters

Volumn 30, Issue 1, 2009, Pages 39-41

  Pan, Tung Ming ^a   Chan, Ching Lin ^a   Wu, Tin Wei ^a  

^a CHANG GUNG UNIVERSITY   (Taiwan)

Author keywords

Gate dielectric; Grain boundary trap state; High kappa; polycrystalline silicon thin film transistor (poly Si TFT); Pr2O3; PrTiO3

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; FLAT PANEL DISPLAYS; GATE DIELECTRICS; GATES (TRANSISTOR); HYDROGENATION; POLYSILICON; SEMICONDUCTING ORGANIC COMPOUNDS; SEMICONDUCTING SILICON; THIN FILM DEVICES; THIN FILM TRANSISTORS; TRANSISTORS;

CURRENT RATIOS; DISPLAY DRIVING CIRCUITS; ELECTRICAL CHARACTERISTICS; GATE CAPACITANCES; GRAIN-BOUNDARY TRAP STATE; HIGH-KAPPA POLYCRYSTALLINE-SILICON THIN-FILM TRANSISTOR (POLY-SI TFT); HYDROGENATION TREATMENTS; LARGER FIELDS; LOW POWERS; PR2O3; PRTIO3; SUBTHRESHOLD SWINGS;

SILICON;

EID: 58149508197     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2008449     Document Type: Article

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