Evaluation of intrinsic parameter fluctuations on 45, 32 and 22nm technology node LP N-MOSFETs

ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference

Volumn , Issue , 2008, Pages 47-50

  Cheng, B ^a   Roy, S ^a   Brown, A R ^a   Millar, C ^a   Asenov, A ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

MOSFET DEVICES; NANOTECHNOLOGY;

BULK COUNTERPARTS; BULK DEVICES; DEVICE ARCHITECTURES; DG MOSFETS; DOUBLE GATES; INTRINSIC PARAMETER FLUCTUATIONS; LINE EDGE ROUGHNESSES; MOS FETS; QUANTITATIVE EVALUATIONS; RANDOM DOPANTS; SIMULATION RESULTS; STATISTICAL VARIABILITIES; TECHNOLOGY NODES; THIN BODIES;

GALERKIN METHODS;

EID: 58049117287     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2008.4681695     Document Type: Conference Paper

References (12)

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2. http://www.itrs.net.
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