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Volumn , Issue , 2005, Pages 264-267

Up to 80-Gbit/s operations of 1:4 Demultiplexer IC with InP HBTs

Author keywords

1:4 Demultiplexer; 80 Gbit s; High Collector Current Density; InP HBT; Multiphase Clock; Pulse Pattern Generators

Indexed keywords

DEMULTIPLEXING; OPTOELECTRONIC DEVICES; SEMICONDUCTING INDIUM PHOSPHIDE;

EID: 30944452189     PISSN: 15508781     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSICS.2005.1531834     Document Type: Conference Paper
Times cited : (6)

References (9)
  • 1
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    • T. Suzuki, et al., "144-Gbit/s Selector and 100-Gbit/s 4:1 Multiplexer Using InP HEMTs", 2004 MTT-S Technical Digest, pp. 117-120 (2004)
    • (2004) 2004 MTT-S Technical Digest , pp. 117-120
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  • 2
    • 10444270913 scopus 로고    scopus 로고
    • A 132-Gbit/s 4:1 multiplexer in 0.13-μm SiGe bipolar technology
    • M. Meghelli, "A 132-Gbit/s 4:1 Multiplexer in 0.13-μm SiGe Bipolar Technology", IEEE J. Solid-State Circuits, Vol. 39, No. 12, pp. 2403-2407 (2004)
    • (2004) IEEE J. Solid-state Circuits , vol.39 , Issue.12 , pp. 2403-2407
    • Meghelli, M.1
  • 3
    • 4444336608 scopus 로고    scopus 로고
    • An 80-Gbit/s 1:2 Demultiplexer in InP-based HEMT technology
    • Y. Nakasha, et al., "An 80-Gbit/s 1:2 Demultiplexer in InP-based HEMT Technology", 2004 RFIC Symposium Technical Digest, pp.321-324 (2004)
    • (2004) 2004 RFIC Symposium Technical Digest , pp. 321-324
    • Nakasha, Y.1
  • 5
    • 0742304084 scopus 로고    scopus 로고
    • 50-Gb/s InP HEMT 4:1 multiplexer / demultiplexer chip set with a multiphase clock architecture
    • K. Sano, etal., "50-Gb/s InP HEMT 4:1 Multiplexer / Demultiplexer Chip Set With a Multiphase Clock Architecture", IEEE Trans, on Microwave Theory and Techniques, Vol. 51, no.12, pp.2548-2554 (2003)
    • (2003) IEEE Trans, on Microwave Theory and Techniques , vol.51 , Issue.12 , pp. 2548-2554
    • Sano, K.1
  • 6
    • 0141606018 scopus 로고    scopus 로고
    • Low-power 50Gbit/s InP HBT 1:4 demultiplexer IC with multiphase clock architecture
    • K. Sano, et al., "Low-power 50Gbit/s InP HBT 1:4 demultiplexer IC with multiphase clock architecture", IEE Electron. Lett., Vol.39, No. 18, pp. 1332-1334 (2003)
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    • Sano, K.1
  • 7
    • 30944450010 scopus 로고    scopus 로고
    • Over-100-Gbit/s multiplexing operation of InP DHBT selector IC designed with high collector-current density
    • K. Sano, et al., "Over-100-Gbit/s Multiplexing Operation of InP DHBT Selector IC Designed with High Collector-Current Density", 2004 International Conference on Solid State Devices and Materials, pp. 312-313 (2004)
    • (2004) 2004 International Conference on Solid State Devices and Materials , pp. 312-313
    • Sano, K.1
  • 8
    • 3142613410 scopus 로고    scopus 로고
    • High-performance composite-collector InP/InGaAs heterojunction bipolar transistors
    • K. Kurishima, et al., "High-performance composite-collector InP/InGaAs heterojunction bipolar transistors", Jpn. J. Appl. Phys., Vol.43, No.4B, pp.2243-2249 (2004)
    • (2004) Jpn. J. Appl. Phys. , vol.43 , Issue.4 B , pp. 2243-2249
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  • 9
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    • InP-based IC technologies for 100-Gbit/s and beyond
    • K. Murata, et al., "InP-based IC technologies for 100-Gbit/s and beyond", 2004 Indium Phosphide and Related Materials, pp. 10-15 (2004)
    • (2004) 2004 Indium Phosphide and Related Materials , pp. 10-15
    • Murata, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.