A 80-Gbit/s D-type flip-flop circuit using InP HEMT technology

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

Volumn , Issue , 2003, Pages 165-168

  Suzuki, T ^a   Takahashi, T ^a   Hirose, T ^a   Takigawa, M ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

80 Gbit s; D type flip flop (D FF); InP HEMT; Rat race

Indexed keywords

DIFFERENTIAL AMPLIFIERS; ELECTRIC POWER SUPPLIES TO APPARATUS; HIGH ELECTRON MOBILITY TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; PHASE CHANGING CIRCUITS; SEMICONDUCTING INDIUM PHOSPHIDE; TRANSCONDUCTANCE;

CUT-OFF FREQUENCY; D-TYPE FLIP FLOP CIRCUIT; DIFFERENTIAL CLOCK SIGNAL; POWER SUPPLY VOLTAGE;

FLIP FLOP CIRCUITS;

EID: 0348195880     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/gaas.2003.1252386     Document Type: Conference Paper

References (5)

1. K. Murata, K. Sano, H. Kitabayashi, S. Sugitani H. Sugahara, and T. Enoki, "100-Gbit/s Logic IC using 0.1-μm-gate-length InAlAs/InGaAs/InP HEMTs," IEDM 2002 Digest pp. 937-939.
2. T. Suzuki, Y. Nakasha, T. Sakoda, K. Sawada, T. Takahashi, K. Makiyama, T. Hirose, and M. Takigawa, "A 100-Gbit/s 2:1 Multiplexer in InP HEMT Technology," 2003 IEEE MTT-S International Microwave Symposium Digest pp 1173-1176
3. M. Mokhtari, C. Fields, and R.D. Rajavel, "100+GHz Static Divide-By-2 Circuit in InP-DHBT Technology," 2002 IEEE GaAs IC Symposium Digest pp 291-293
4. K. Murata T. Otsuji, E. Sano, S. Kimura, and Y. Yamane, "70-Gbit/s Multiplexer and 50-Gbit/s Decision IC Modules Using InAlAs/InGaAs/InP HEMTs," IEICE TRANS. ELECTRON., Vol.E83-C, No. 7 July 2000.
5. Y. Kuriyma, T. Sugiyama, S. Hongo, J. Akagi, N. Iizuka and M. Obara, "A 40-GHz D-type Flip-Flop Using AlGaAs/GaAs HBT's," IEEE Journal of Solid-State Circuits. Vol. 30, No. 10, Oct. 1995 pp 1128-1130.