90Gbit/s 0.5 W decision circuit using InP/InGaAs double heterojunction bipolar transistors

Electronics Letters

Volumn 40, Issue 16, 2004, Pages 1020-1021

  Ishii, K ^a   Sano, K ^a   Murata, K ^a   Ida, M ^a   Kurishima, K ^a   Shibata, T ^a   Enoki, T ^a   Sugahara, H ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CARRIER CONCENTRATION; FLIP FLOP CIRCUITS; FREQUENCIES; OPTICAL COMMUNICATION; OSCILLATIONS; SEMICONDUCTING INDIUM COMPOUNDS; SENSITIVITY ANALYSIS;

CLOCK BUFFERS; DATA BUFFERS; ON-CHIP RESISTORS; OUTPUT BUFFERS;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 4043164235     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20045280     Document Type: Article

References (4)

1. max InP/InGaAs double heterojunction bipolar transistors with a thin pseudomorphic base', IEEE Electron Device Lett., 2002, 23, pp. 694-696
2. Suzuki, T., Takahashi, T., Hirose, T., and Takigawa, M.: 'A 80-Gbit/s D-type flip-flop circuit using InP HEMT technology'. GaAs Integrated Circuits Symp., 25th Annual Tech. Dig., San Diego, CA, USA, 2003, pp. 165-168
3. Ishii, K., Ichino, H., Togashi, M., Kobayashi, Y., and Yamaguchi, C.: 'Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops', IEEE J. Solid-State Circuits, 1995, 30, pp. 19-24
4. Murata, K., Sano, K., Enoki, T., Sugahara, H., and Tokumitsu, M.: "InP-based IC technologies for 100-Gbit/s and beyond'. Tech. Dig. of 16th Int. Conf. on Indium Phosphide and Related Materials (IPRM'04), Kagoshima, Japan, 2004, Paper TuA-1-1