Low-spur, low-phase-noise clock multiplier based on a combination of PLL and recirculating DLL with dual-pulse ring oscillator and self-correcting charge pump

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 12, 2008, Pages 2967-2976

  Gierkink, Sander L J ^a,b  

^a Conexant Systems ^*  (United States)

^b Axiom IC Twente   (Netherlands)

Author keywords

Charge pump; Delay locked loops; Phase noise; Phase locked loops; Voltage controlled oscillators

Indexed keywords

CLOCKS; DELAY CIRCUITS; ELECTRIC CONVERTERS; FREQUENCY MULTIPLYING CIRCUITS; PHASE LOCKED LOOPS; PHASE NOISE; PUMPS; SPURIOUS SIGNAL NOISE;

90NM CMOS; CHARGE PUMP; CLOCK MULTIPLIERS; DELAY-LOCKED LOOPS; LOW PHASE NOISES; PHASE INDEPENDENTS; REFERENCE SPURS; RING OSCILLATORS; STATIC PHASE OFFSETS; VOLTAGE-CONTROLLED OSCILLATORS;

OSCILLATORS (ELECTRONIC);

EID: 57849086993     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2006225     Document Type: Conference Paper

References (15)

1. F. M. Gardner, "Charge-pump phase-lock loops." IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, Nov. 1980.
2. R. Farjad-Rad et al., "A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips", IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1804-1812, Dec. 2002.
3. P. C. Maulik and D. A. Mercer, "A DLL-based programmable clock multiplier in 0.18-μm CMOS with -70 dBc reference spur", IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1642-1648, Aug. 2007.
4. S. Ye and I. Galton. "Techniques for phase noise suppression in recirculating DLLs", IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1222-1230, Aug. 2004.
5. G. Chien and P. R. Gray, "A 900-MHz local oscillator using a DLL- based frequency multiplier technique for PCS applications", IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1996-1999, Dec. 2000.
6. C. N. Chuang and S. I. Liu, "A 40 GHz DLL-based clock generator in 90 nm CMOS technology", in IEEE ISSCC 20007 Dig. Tech. Papers, Feb. 2007, pp. 178-179.
7. V. J. Arkesteijn, E. A. M. Klumperink, and B. Nauta, "Jitter requirements of the sampling clock in software radio receivers", IEEE Trans. Circuits Syst. II: E. xpr. Briefs, vol. 53, no. 2, pp. 90-94, Feb. 2006.
8. Q. Du, J. Zhuang, and T. Kwasniewski, "A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction", IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 53, no. 11, pp. 1205-1209, Nov. 2006.
9. B. M. Helal, M. Z. Straayer, G.-Y. Wei, and M. H. Perrott, "A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance", IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 855-863, Apr. 2008.
10. S. L. J. Gierkink, "An 800 MHz-122 dBc/Hz 200 kHz clock multiplier based on a combination of PLL and recirculating DLL", in IEEE ISSCC 2008 Dig. Tech. Papers, Feb. 2008, pp. 454-455.
11. S. L. J. Gierkink, "A 2.5 Gb/s run length tolerant burst-mode CDR based on a 1/8th-rate dual pulse ring oscillator", IEEE J. Solid-State Circuits, vol. 43, no. 8, pp. 1763-1771, Aug. 2008.
12. A. Han-Yuan and G.-Y. Wei, "Adaptive-bandwidth mixing PLL/DLL based multi-phase clock generator for optimal jitter performance", in Proc. 2006 IEEE Custom Integrated Circuits Conf., Sep. 2006, pp. 749-752.
13. S. L. J. Gierkink and A. J. M. van Tuijl, "A coupled sawtooth oscillator combining low jitter with high control linearity", IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 702-710, Jun. 2002'.
14. C. N. Chuang and S. I. Liu, "A 0.5-5 GHz wide-range multiphase DLL with a calibrated charge pump", IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 54, no. 11, pp. 939-943, Nov. 2007.
15. W. A. Gardner and L. E. Franks, "Characterization of cyclostationary random signal processes", IEEE Trans. Inf. Theory, vol. IT-21, no. 1, pp. 4-14, Jan. 1975.