Jitter Requirements of the Sampling Clock in Software Radio Receivers

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 53, Issue 2, 2006, Pages 90-94

  Arkesteijn, Vincent J ^a   Klumperink, Eric A M ^a   Nauta, Bram ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

Analog to digital converter (ADC); jitter; mixer; sampling; software radio

Indexed keywords

ANALOG TO DIGITAL CONVERSION; HETERODYNING; MIXER CIRCUITS; SPECTRUM ANALYSIS; TIMING JITTER;

CHANNEL BANDWIDTH; ERROR SIGNAL; INPUT SIGNAL; QUANTIZATION NOISE; QUANTIZATION STEP INACCURACY; SAMPLING CLOCK; SAMPLING TIME UNCERTAINTY; SOFTWARE RADIO RECEIVERS;

RADIO RECEIVERS;

EID: 33144463702     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2005.856893     Document Type: Article

References (12)

1. K. Muhammad et al., “A discrete-time bluetooth receiver in a 0.13 pm digital CMOS process,” in Proc. IEEE Int. Solid-State Circuits Conf., 2004, pp. 268–269.
2. V. J. Arkesteijn, E. A. M. Klumperink, and B. Nauta, “ADC clock jitter requirements for software radio receivers,” in Proc. IEEE 60th Veh. Technol. Conf., Sep. 2004, pp. 1983–1985.
3. R. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters. Norwell, MA: Kluwer, 1994.
4. D. H. Shen, C.-M. Hwang, B. B. Lusignan, and B. A. Wooley, “A 900-MHz RF front-end with integrated discrete-time filtering,” IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1945–1954, Dec. 1996.
5. M. Shinagawa, Y. Akazawa, and T. Wakimoto, “Jitter analysis of high-speed sampling systems,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 220–224, Feb. 1990.
6. M. Patel, I. Darwazeh, and J. J. O’Reilly, “Bandpass sampling for software radio receivers, and the effect of oversampling on aperture jitter,” in Proc. 55th Veh. Technol. Conf., May 2002, pp. 1901–1905.
7. N. Da Dalt, M. Harteneck, C. Sandner, and A. Wiesbauer, “On the jitter requirements of the sampling clock for analog-to-digital converters,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 49, no. 9, pp. 1354–1360, Sep. 2002.
8. B.-S. Song, “High-speed pipelined ADC,” in Eur. Solid-State Circuits Conf. Tutorial, Florence, Italy, Sep. 2002.
9. S. Lindfors, A. Pärssinen, and K. A. I. Halonen, “A 3-V 230-MHz CMOS decimation subsampler,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 3, pp. 105–117, Mar. 2003.
10. ETSI TS 101 475 v1.2.2 (2001-02) Technical Specification Broadband Radio Access Networks (BRAN); HIPERLAN Type 2; Physical (PHY) Layer, 2001–2002.
11. B. Razavi, RE Microelectronics. Englewood Cliffs, NJ: Prentice-Hall, 1998.
12. D. C. Lee, “Analysis of jitter in phase-locked loops,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 11, pp. 704–711, Nov. 2002.