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Volumn 43, Issue 8, 2008, Pages 1763-1771

A 2.5 Gb/s run-length-tolerant burst-mode CDR based on a 1/8th-rate dual pulse ring oscillator

Author keywords

Clock and data recovery (CDR); Phase locked loop (PLL); Voltage controlled oscillator (VCO)

Indexed keywords

CLOCKS; DATA ACQUISITION;

EID: 48849093545     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.926736     Document Type: Conference Paper
Times cited : (13)

References (9)
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  • 2
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  • 3
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    • A 2.5Gb/s burst-mode CDR based on a 1/8th rate dual pulse ring oscillator
    • Sep
    • S. L. J. Gierkink, "A 2.5Gb/s burst-mode CDR based on a 1/8th rate dual pulse ring oscillator," in Proc. IEEE CICC, Sep. 2007, pp. 357-360.
    • (2007) Proc. IEEE CICC , pp. 357-360
    • Gierkink, S.L.J.1
  • 4
    • 0036612166 scopus 로고    scopus 로고
    • A coupled sawtooth oscillator combining low jitter with high control linearity
    • Jun
    • S. L. J. Gierkink and A. J. M. van Tuijl, "A coupled sawtooth oscillator combining low jitter with high control linearity," IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 702-710, Jun. 2002.
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  • 5
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    • Jul
    • M. P. Flynn and S. U. Lidholm, "A 1.2-μm CMOS current-controlled oscillator," IEEE J. Solid-State Circuits, vol. 27, no. 7, pp. 982-987, Jul. 1992.
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  • 6
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    • Ph.D. dissertation, Politecnico di Milano, Milan, Italy
    • S. Pellerano, "Fully-integrated frequency synthesizers for multi-standard WLAN applications," Ph.D. dissertation, Politecnico di Milano, Milan, Italy, 2004.
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    • Pellerano, S.1
  • 7
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    • A multiple-crystal interface PLL with VCO realignment to reduce phase noise
    • Dec
    • S. Ye, L. Jansson, and I. Galton, "A multiple-crystal interface PLL with VCO realignment to reduce phase noise," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1795-1803, Dec. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.12 , pp. 1795-1803
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  • 8
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    • R. Farjad-Rad et al., "A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1804-1812, Dec. 2002.
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  • 9
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    • An 800 MHz -122 dBc/Hz @ 200 kHz clock multiplier based on a combination of PLL and recirculating DLL
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.