Adaptive-bandwidth mixing PLL/DLL based multi-phase clock generator for optimal jitter performance

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 749-752

  Tan, Amber Han Yuan ^a   Wei, Gu Yeon ^a  

^a HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE BANDWIDTH MIXING; OPTIMAL JITTER PERFORMANCE; PHASE ROTATOR;

ADAPTIVE SYSTEMS; BANDWIDTH; OPTIMAL SYSTEMS;

JITTER;

EID: 39049161080     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320967     Document Type: Conference Paper

References (6)

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2. R. Farjad-Rad, et al., "A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os," IEEE Journal of Solid-State Circuits, vol. 39, pp. 1553-1561, Sept. 2004.
3. S. Sidiropoulos and M. Horowitz, "A semidigital dual delay-locked loop," IEEE Journal of Solid-State Circuits, Nov. 1997.
4. G.-Y. Wei, et al., "A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25μm CMOS," ISSCC Dig. of Tech Papers, pp. 464-465, Feb. 2003.
5. P. Larsson, "A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability," IEEE Journal of Solid-State Circuits, vol. 34, pp. 1951-1960, Dec. 1999.
6. Y.-C. Bae and G.-Y. Wei, "A mixed PLL/DLL architecture for low jitter clock generation," ISCAS '04 Proc. pp. 788-791, May 2004.